From patchwork Thu Jul 29 01:12:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 488807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77A62C4338F for ; Thu, 29 Jul 2021 01:13:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C82B61059 for ; Thu, 29 Jul 2021 01:13:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233277AbhG2BNy (ORCPT ); Wed, 28 Jul 2021 21:13:54 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:64145 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233240AbhG2BNx (ORCPT ); Wed, 28 Jul 2021 21:13:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1627521231; x=1659057231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Ovw9WoZ0YrotwnPUK4JwpO7mOXRMGw27QHpFWOln15I=; b=Ficx/77DJdeWqcQ8qpgWP+NIU+WKNd7e79FXDmulb7Retq897HDgxeix Q074LRc0B7M7NZ9w4MW0NjplAep7RjqdaYZm0oeD6TdD39EPDnkp3tRG4 9gzdtizx2dR6+BaQVW33oAnGac43Y1JFw9xtQ63QvsfH+MKtUqMQQ2vrs M=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Jul 2021 18:13:51 -0700 X-QCInternal: smtphost Received: from nasanexm03e.na.qualcomm.com ([10.85.0.48]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/AES256-SHA; 28 Jul 2021 18:13:51 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nasanexm03e.na.qualcomm.com (10.85.0.48) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Wed, 28 Jul 2021 18:13:48 -0700 From: Fenglin Wu To: , , CC: , , , Ashay Jaiswal Subject: [PATCH V1 4/9] spmi: pmic-arb: add support to dispatch interrupt based on IRQ status Date: Thu, 29 Jul 2021 09:12:42 +0800 Message-ID: <1627521167-18848-5-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627521167-18848-1-git-send-email-quic_fenglinw@quicinc.com> References: <1627521167-18848-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanexm03e.na.qualcomm.com (10.85.0.48) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Ashay Jaiswal Current implementation of SPMI arbiter dispatches interrupt based on the Arbiter's accumulator status, in some cases the accumulator status may remain zero and the interrupt remains un-handled. Add logic to dispatch interrupts based Arbiter's IRQ status if the accumulator status is zero. Signed-off-by: Ashay Jaiswal Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index c4adc06..59c445b 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -525,12 +525,18 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) u8 ee = pmic_arb->ee; u32 status, enable; int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; chained_irq_enter(chip, desc); for (i = first; i <= last; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; status &= ~BIT(id); @@ -548,6 +554,28 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = pmic_arb->min_apid; i <= pmic_arb->max_apid; i++) { + /* skip if APPS is not irq owner */ + if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee) + continue; + + irq_status = readl_relaxed( + ver_ops->irq_status(pmic_arb, i)); + if (irq_status) { + enable = readl_relaxed( + ver_ops->acc_enable(pmic_arb, i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pmic_arb->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + periph_interrupt(pmic_arb, i); + } + } + } + } + chained_irq_exit(chip, desc); }