From patchwork Tue Oct 18 07:25:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 77928 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp748183qge; Tue, 18 Oct 2016 00:25:50 -0700 (PDT) X-Received: by 10.98.131.71 with SMTP id h68mr2334990pfe.166.1476775550827; Tue, 18 Oct 2016 00:25:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c72si30904653pga.56.2016.10.18.00.25.50; Tue, 18 Oct 2016 00:25:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758595AbcJRHZu (ORCPT + 10 others); Tue, 18 Oct 2016 03:25:50 -0400 Received: from mail-lf0-f49.google.com ([209.85.215.49]:34708 "EHLO mail-lf0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755072AbcJRHZt (ORCPT ); Tue, 18 Oct 2016 03:25:49 -0400 Received: by mail-lf0-f49.google.com with SMTP id b81so329023055lfe.1 for ; Tue, 18 Oct 2016 00:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=rqYYCMEJd7HFZ9bz4Du/styKkYr6vnu6cwJma2GZUeg=; b=dMXA75MyGG0FE0OeeXG2lJbDVPgJGqwzfMQgvqBcrU/N6kjmL0gmUVUlFM8XoFNA+a G06s7RuLh7//NpjhgKDlX87ueFD9G694ie25bA0eKUqscPmWOKEehLwvWCczLTYmCAhZ plOLImrMS8RxzsZzqDVdqHuHPz4IIMVkJDMf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rqYYCMEJd7HFZ9bz4Du/styKkYr6vnu6cwJma2GZUeg=; b=aimfhdoTFUc5rpAWtlNiSIIsVq5A5YDUyc1OU2/0blG4POlc6pelZ+EIXV8YKiKik7 vXOdteYtAfrkj1uzws4mOhhLghjpWmbWYPF7ThB1ui7YbbUIy7xhYozvz0Dcx7UJmrh3 8uI8oNk2zR89fPEoBI1PkuM6Q0TApRcsMT2mDNUuSy+f8vPAbkBFgrUsRoD1BgtYQtmN p8P2AdVcXri7+qosaLvS+J4VfrX62soHrEBjaqkiku17VSoO5vROAZodF5DMcJybVR9y 4GEHNvvv1HIiOi628b2FXs72dAtG8sGjIQWq3iAL4Jo2Hkzpj0lG21+ispNmpDfBvCzb bbLA== X-Gm-Message-State: AA6/9RnpvZyZebuXRoGZX4KMz9a2mAl33pPrbvp80k1fhxJ645kAzQWbYotZHGgChnsanD4S X-Received: by 10.25.25.84 with SMTP id 81mr11947083lfz.26.1476775545864; Tue, 18 Oct 2016 00:25:45 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id l202sm4482657lfb.47.2016.10.18.00.25.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Oct 2016 00:25:45 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross Cc: Stephen Boyd , Bjorn Andersson , David Brown , Linus Walleij Subject: [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard Date: Tue, 18 Oct 2016 09:25:42 +0200 Message-Id: <1476775542-4540-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SMSC9112 ethernet controller is connected to chip select 2 on the EBI2 bus on the APQ8060 Dragonboard. We set this up by activating EBI2, creating a chipselect entry as a subnode, and then putting the ethernet controller in a subnode of the chipselect. After the chipselect is configured, the SMSC device will be instantiated. Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Rebase on kernel v4.9-rc1 - Bindings and driver are merged so should be clear to apply. ChangeLog v2->v3: - Name chipselected device to ethernet-ebi2@2,0 - Update to the latest (v5) version of the bindings and what the EBI2 driver expects. - The SMSC911x bindings were ACKed by Arnd Bergmann and are merged to the netdev tree by David Miller. - The EBI2 bindings were ACKed by Rob Herring and a pull request for both bindings and driver is pending for ARM SoC. - This should be safe to merge for v4.9. ChangeLog v1->v2: - Use the new bindings with the first address cell indicating the chipselect - Use offset zero into the range in the EBI2 node (the range defines the base address of the chipselect) - Move all the XMEM setup to arrays in the EBI2 node --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 124 +++++++++++++++++++++++++ 1 file changed, 124 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 6c0038398ef2..7848e4c8bdb9 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -51,6 +51,29 @@ regulator-boot-on; }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; + + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; + /* This is a levelshifter for SDCC5 */ dragon_vio_txb: txb0104rgyr { compatible = "regulator-fixed"; @@ -167,6 +190,41 @@ bias-pull-up; }; }; + + dragon_ebi2_pins: ebi2 { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * only CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + mux0 { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * only CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + pins = + /* "gpio39", CS1A_N this is not good to mux */ + "gpio40", /* CS2A_N */ + "gpio134"; /* CS0_N testpoint TP29 */ + function = "ebi2cs"; + }; + mux1 { + pins = + /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ + "gpio135", "gpio136", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", + "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", + "gpio151", /* EBI2_OE_N */ + "gpio153", /* EBI2_ADV */ + "gpio157"; /* EBI2_WE_N */ + function = "ebi2"; + }; + }; }; qcom,ssbi@500000 { @@ -201,6 +259,15 @@ }; gpio@150 { + dragon_ethernet_gpios: ethernet-gpios { + pinconf { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; dragon_bmp085_gpios: bmp085-gpios { pinconf { pins = "gpio16"; @@ -238,6 +305,14 @@ power-source = ; }; }; + dragon_veth_gpios: veth-gpios { + pinconf { + pins = "gpio40"; + function = "normal"; + bias-disable; + drive-push-pull; + }; + }; }; led@48 { @@ -322,6 +397,55 @@ }; }; + ebi2@1a100000 { + /* The EBI2 will instantiate first, then populate its children */ + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ebi2_pins>; + + /* + * An on-board SMSC LAN9221 chip for "debug ethernet", + * which is actually just an ordinary ethernet on the + * EBI2. This has a 25MHz chrystal next to it, so no + * clocking is needed. + */ + ethernet-ebi2@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + /* + * GPIO7 has interrupt 198 on the PM8058 + * The second interrupt is the PME interrupt + * for network wakeup, connected to the TLMM. + */ + interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&dragon_veth>; + vddvario-supply = <&dragon_vario>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ethernet_gpios>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + /* IRQ on edge falling = active low */ + smsc,irq-active-low; + smsc,irq-push-pull; + + /* + * SLOW chipselect config + * Delay 9 cycles (140ns@64MHz) between SMSC + * LAN9221 Ethernet controller reads and writes + * on CS2. + */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; + }; + rpm@104000 { /* * Set up of the PMIC RPM regulators for this board