From patchwork Fri Aug 26 20:17:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 74845 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp544502qga; Fri, 26 Aug 2016 13:19:42 -0700 (PDT) X-Received: by 10.66.49.67 with SMTP id s3mr9326724pan.100.1472242751841; Fri, 26 Aug 2016 13:19:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y80si22825624pfi.205.2016.08.26.13.19.11; Fri, 26 Aug 2016 13:19:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752977AbcHZUTI (ORCPT + 8 others); Fri, 26 Aug 2016 16:19:08 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35565 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753419AbcHZUTG (ORCPT ); Fri, 26 Aug 2016 16:19:06 -0400 Received: by mail-pf0-f181.google.com with SMTP id x72so31719065pfd.2 for ; Fri, 26 Aug 2016 13:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4ybmnCVy42PgqHAJ+e4IXG9uE3IMbmRdOsfLVs16t7o=; b=f84TQwQArw7lKRmbQfP4lUC2NYoJN9Q2GRgxLSr8TeWCzRBlxDEkjfCqIwHekerur+ Y6crH6oFrYJfokr4C/ax9fstEDIh2nbEqwFCkgYAtrFa0aOK/yzSYYgmk4Oe/ivcXGQ9 tSp/R5Jyf6BsRYR2/SoJwkuQ063/7gyd0viqY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4ybmnCVy42PgqHAJ+e4IXG9uE3IMbmRdOsfLVs16t7o=; b=fCjcB5tYLKGoYaoB4aCApPs9f09AxbEjcr6bdCJfp5RPMel2Tbw/offdUP2sNFFRMq TfSLOJlgDHwgKGR3A9YS3csO4RCsF6P3Sz7KEJHoI/1mO5hTk71s0PtyBZ48Z0ioLNrK AL1IDgdEQ1jaA0oDx54GKHaBkKgKypDHt4+vwJ8Xl9M/Av7BQViHyUM3yDTJezmjeI6y lmF7lIMHvvezxLSvH6NK8V4dBhB8du1kYxkKZJKDM1Oz2sUBxWovHIsaI9aDTrwjxW6n biw3hyFke4MDAmFgv5pwEL5QzcvgNjpxRLrGzk817Ovput9BSqR6KPrPJIBWC6gH90tN pl6Q== X-Gm-Message-State: AE9vXwPGT0W6ujF6so4mL0qQHBk8ClNYVjdbXpjjtCfktxoivFVOZQxAmSHFzOpH28pSA4GY X-Received: by 10.98.57.151 with SMTP id u23mr9305392pfj.4.1472242731960; Fri, 26 Aug 2016 13:18:51 -0700 (PDT) Received: from ubuntu.localdomain (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id m128sm30761463pfm.42.2016.08.26.13.18.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Aug 2016 13:18:50 -0700 (PDT) From: Lina Iyer To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: andy.gross@linaro.org, sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org, brendan.jackman@arm.com, lorenzo.pieralisi@arm.com, sudeep.holla@arm.com, Juri.Lelli@arm.com, Lina Iyer , devicetree@vger.kernel.org, Mark Rutland Subject: [PATCH v5 15/16] dt/bindings: Add PSCI OS-Initiated PM Domains bindings Date: Fri, 26 Aug 2016 14:17:57 -0600 Message-Id: <1472242678-33700-16-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472242678-33700-1-git-send-email-lina.iyer@linaro.org> References: <1472242678-33700-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for defining a OS-Initiated based CPU PM domain. Cc: Cc: Lorenzo Pieralisi Cc: Mark Rutland Signed-off-by: Lina Iyer --- Documentation/devicetree/bindings/arm/psci.txt | 79 ++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d..63a229b 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,86 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPU domains +from the firmware. Such PM domains for which the PSCI firmware driver acts as +pseudo-controller, may also be specified in the DT under the psci node. The +domain definitions must follow the domain idle state specifications per [3]. +The domain states themselves must be compatible with 'arm,idle-state' defined +in [1] and need to specify the arm,psci-suspend-param property for each idle +state. + +More information on defining CPU PM domains is available in [4]. + +Example: OS-Iniated PSCI based PM domains with 1 CPU in each domain + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>; + power-domains = <&CPU_PD0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>; + power-domains = <&CPU_PD1>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_gdhs { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd@0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>; + }; + + CPU_PD1: cpu-pd@1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DWN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt +[4]. CPU PM Domains description + Documentation/power/cpu_domains.txt