From patchwork Thu Aug 25 11:20:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 74674 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp784764qga; Thu, 25 Aug 2016 04:21:07 -0700 (PDT) X-Received: by 10.98.95.129 with SMTP id t123mr15143137pfb.148.1472124066985; Thu, 25 Aug 2016 04:21:06 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p184si15121994pfb.299.2016.08.25.04.21.06; Thu, 25 Aug 2016 04:21:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757646AbcHYLVF (ORCPT + 8 others); Thu, 25 Aug 2016 07:21:05 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:36883 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757301AbcHYLVE (ORCPT ); Thu, 25 Aug 2016 07:21:04 -0400 Received: by mail-wm0-f44.google.com with SMTP id i5so66578953wmg.0 for ; Thu, 25 Aug 2016 04:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=XVd01UrmxlYn79ud3wZChboww7l2i3kqKqueeNnuv5g=; b=SiT/IkgtqFsySWcdDCfixSLQClWhaMoD+lYOLZYcTzhQiUNY2lJq/Uxjw5tHB/qNkJ Xg1f+isvZlyY9k2txOS96kCvYJDDibmt/r7UZdd+qRq9VIjvG4ImnlYBzVR8re8hSMu6 6WGyn7/2tu866BdNdjQc7P8o6qU7cWirp/tfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XVd01UrmxlYn79ud3wZChboww7l2i3kqKqueeNnuv5g=; b=E3gsRks3tS5PaxAJHKBy9n0g/2WXoWnNB30uX9Y51Lg8ZxwA7gXZ/a0s+21XNf89eC YCzOsLNansku1b1tIr6zpi1H54iGlsIsvecn3vyUdrduOlxAajLkFGwmsi9i/DtEcVY1 PMW5DdaNdTmJ3GR9R0bhwjQW+G7nOqyiO5u57veNTnMxqv9Gp48CFxGc+H57lV8VeVhL QlPojB6f1m7Ayey+B6twGfWBgwTzONLDn4XIX9ILcAvqEWmyL3GFbGgcXDx5JOBZtd64 OLXMnRVXvIWUDMz24Jb+/To/jg7PhDa2xiIkMIDlxrQvT0g/EloyTrKK5+v2xcYc3Zmw DiQQ== X-Gm-Message-State: AE9vXwPNd4yEBoQeWXEGT8C/W65N1zFIN7aEBDKKbskDNiEaoNjf4Il4tI6oEcYnGcLY6qPV X-Received: by 10.28.12.76 with SMTP id 73mr7306712wmm.118.1472124063378; Thu, 25 Aug 2016 04:21:03 -0700 (PDT) Received: from localhost.localdomain (host-2-103-180-164.as13285.net. [2.103.180.164]) by smtp.gmail.com with ESMTPSA id o4sm14643695wjd.15.2016.08.25.04.21.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Aug 2016 04:21:02 -0700 (PDT) From: Srinivas Kandagatla To: Stephen Boyd Cc: Andy Gross , David Brown , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/2] clk: gcc-msm8996: Fix pcie 2 pipe register offset Date: Thu, 25 Aug 2016 12:20:46 +0100 Message-Id: <1472124047-22627-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/gcc-msm8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index a1ef12f..456b2f4 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { }; static struct clk_branch gcc_pcie_2_pipe_clk = { - .halt_reg = 0x6e108, + .halt_reg = 0x6e018, .clkr = { - .enable_reg = 0x6e108, + .enable_reg = 0x6e018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk",