From patchwork Fri Jun 24 15:07:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 70827 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp996618qgy; Fri, 24 Jun 2016 08:07:22 -0700 (PDT) X-Received: by 10.98.97.193 with SMTP id v184mr8296292pfb.138.1466780842628; Fri, 24 Jun 2016 08:07:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cz10si7229862pad.214.2016.06.24.08.07.22; Fri, 24 Jun 2016 08:07:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751298AbcFXPHU (ORCPT + 8 others); Fri, 24 Jun 2016 11:07:20 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:35965 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751072AbcFXPHS (ORCPT ); Fri, 24 Jun 2016 11:07:18 -0400 Received: by mail-wm0-f52.google.com with SMTP id f126so26012450wma.1 for ; Fri, 24 Jun 2016 08:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=8Q+LWwnalglP4UCeQVfKYjqNR1OHxX3pEPqaDMJAH4c=; b=A5cpZAPljl+NLP2oCWzPnJ66bnXdLq2Vf1RyKocXcktjUMNpc8YtR+w1drc8CL5qgE NPQWyRBfUGcc4xQ8nw3DX2wxoy0J6EYOOLSitafgGOr9sEc3WEt8DifXVA1H36pg/jO7 IIVZ2yP1KGz9Nb9+o/VsNUjLLtaMzkrfVWZRU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8Q+LWwnalglP4UCeQVfKYjqNR1OHxX3pEPqaDMJAH4c=; b=SJlrOv6wfq0Kf0XeruxIcYoaFgdGJBalqgcQPXpn9EffLvcJE5bWeac5ntqwk3y4IJ qMCDPFepMv3EzIm8Gc6SJu6fuKXSvMdJeb+WnkR7spnEK4rC2PNevJH4npFu0Y3+Q3aM 0XDuzDa4ynj8yiYP75c4PID9ACnm5gu7SXxYikElb1oKk3wUMtailt2zcZzmfiQNVwjK sg/43g031k/Y3Y+P6TdKZ3L2r9J+/jFUP26V0lDbVPa2xKjxl92WVGL4LJipZhV63MnB W8yKupkwkkbmDIt72mcalt83M6xj4STtxliWjWlJtRgVj6AYw3NahLppFsk5I7MfQeG1 sjsA== X-Gm-Message-State: ALyK8tI0eEI59sOfIJB98wfm3ns8IKlvWv+gquqZa1GvS2Hcuh/gkmDqRuAXAPG9V5X9AD4Y X-Received: by 10.28.217.146 with SMTP id q140mr19651216wmg.56.1466780836942; Fri, 24 Jun 2016 08:07:16 -0700 (PDT) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id x128sm3570974wmf.6.2016.06.24.08.07.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Jun 2016 08:07:15 -0700 (PDT) From: Georgi Djakov To: ulf.hansson@linaro.org Cc: adrian.hunter@intel.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH] mmc: sdhci-msm: Add support for UHS cards Date: Fri, 24 Jun 2016 18:07:14 +0300 Message-Id: <1466780834-1041-1-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enabling support for ultra high speed mode cards requires some voltage switching and interaction with the PMIC via a special power IRQ. Add support for this. Signed-off-by: Georgi Djakov --- drivers/mmc/host/sdhci-msm.c | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 0653fe730150..ac5700233e12 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -32,6 +32,21 @@ #define CORE_POWER 0x0 #define CORE_SW_RST BIT(7) +#define CORE_PWRCTL_STATUS 0xdc +#define CORE_PWRCTL_MASK 0xe0 +#define CORE_PWRCTL_CLEAR 0xe4 +#define CORE_PWRCTL_CTL 0xe8 +#define CORE_PWRCTL_BUS_OFF BIT(0) +#define CORE_PWRCTL_BUS_ON BIT(1) +#define CORE_PWRCTL_IO_LOW BIT(2) +#define CORE_PWRCTL_IO_HIGH BIT(3) +#define CORE_PWRCTL_BUS_SUCCESS BIT(0) +#define CORE_PWRCTL_IO_SUCCESS BIT(2) +#define REQ_BUS_OFF BIT(0) +#define REQ_BUS_ON BIT(1) +#define REQ_IO_LOW BIT(2) +#define REQ_IO_HIGH BIT(3) +#define INT_MASK 0xf #define MAX_PHASES 16 #define CORE_DLL_LOCK BIT(7) #define CORE_DLL_EN BIT(16) @@ -56,6 +71,7 @@ struct sdhci_msm_host { struct platform_device *pdev; void __iomem *core_mem; /* MSM SDCC mapped address */ + int pwr_irq; /* power irq */ struct clk *clk; /* main SD/MMC bus clock */ struct clk *pclk; /* SDHC peripheral bus clock */ struct clk *bus_clk; /* SDHC bus voter clock */ @@ -410,6 +426,39 @@ retry: return rc; } +static void sdhci_msm_voltage_switch(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + u32 irq_status, irq_ack = 0; + + irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); + irq_status &= INT_MASK; + + writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); + + if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) + irq_ack |= CORE_PWRCTL_BUS_SUCCESS; + if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) + irq_ack |= CORE_PWRCTL_IO_SUCCESS; + + /* + * The driver has to acknowledge the interrupt, switch voltages and + * report back if it succeded or not to this register. The voltage + * switches are handled by the sdhci core, so just report success. + */ + writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); +} + +static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) +{ + struct sdhci_host *host = (struct sdhci_host *)data; + + sdhci_msm_voltage_switch(host); + + return IRQ_HANDLED; +} + static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, {}, @@ -423,6 +472,7 @@ static const struct sdhci_ops sdhci_msm_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_msm_voltage_switch, }; static const struct sdhci_pltfm_data sdhci_msm_pdata = { @@ -545,6 +595,22 @@ static int sdhci_msm_probe(struct platform_device *pdev) CORE_VENDOR_SPEC_CAPABILITIES0); } + /* Setup IRQ for handling power/voltage tasks with PMIC */ + msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); + if (msm_host->pwr_irq < 0) { + dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", + msm_host->pwr_irq); + goto clk_disable; + } + + ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, + sdhci_msm_pwr_irq, IRQF_ONESHOT, + dev_name(&pdev->dev), host); + if (ret) { + dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); + goto clk_disable; + } + ret = sdhci_add_host(host); if (ret) goto clk_disable;