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[213.113.124.204]) by smtp.gmail.com with ESMTPSA id o7sm2366292lfg.45.2016.06.17.13.28.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Jun 2016 13:28:28 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Andy Gross Cc: Stephen Boyd , Bjorn Andersson , David Brown , Linus Walleij Subject: [PATCH 4/7] ARM: dts: add I2C block in GSBI12 Date: Fri, 17 Jun 2016 22:28:09 +0200 Message-Id: <1466195292-28236-6-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1466195292-28236-1-git-send-email-linus.walleij@linaro.org> References: <1466195292-28236-1-git-send-email-linus.walleij@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The I2C block on the GSBI12 is used on the APQ8060 Dragonboard for sensors. Make it available in the chipset file. Take this opportunity to fix the IRQ flag "0" to "NONE" using the IRQ DT include. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/qcom-msm8660.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.4.11 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index e7c6e2942f47..8ee3045f4066 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -122,11 +122,22 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; + interrupts = <0 195 IRQ_TYPE_NONE>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; }; + + gsbi12_i2c: i2c@19c80000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19c80000 0x1000>; + interrupts = <0 196 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; qcom,ssbi@500000 {