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[209.132.180.67]) by mx.google.com with ESMTP id u84si3535968pfi.160.2015.12.14.05.58.36; Mon, 14 Dec 2015 05:58:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751074AbbLNN6e (ORCPT + 6 others); Mon, 14 Dec 2015 08:58:34 -0500 Received: from mail-wm0-f50.google.com ([74.125.82.50]:38602 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932525AbbLNN6X (ORCPT ); Mon, 14 Dec 2015 08:58:23 -0500 Received: by wmpp66 with SMTP id p66so61936272wmp.1 for ; Mon, 14 Dec 2015 05:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GJ0DCk1O6d5H3VZpNRGMlpZR8WwMvQ0AvTbFiTiGIgA=; b=Yb3LTZPlYEVMzgSl1rQzwSqBvpCHb9U1+LtrrDTI21XPGopfHMxhU6Sl//FgYEZYMb WeQwaVRlDTRwA6Hudd4KF2oQGRWiH7LvuW4kf46apSZY2cXFMfZTdLw7BWgkcNR9TRRj R4Oe82j6BjCo+mHQ+wc87Gjr5vkhYIhW9kpKkERfm7zRLyNBBtmJ90U5j/D+hxFSNiW7 2akYe8MobSod3eBB6hV3Hu5dE+q8+e3yt1RT726vtifWOJosH/pWYGCqWZgco14iwAWH 4+rHLuzgj5xhyLjLMcHGH4X3mM49QAi5QrdVmO3WkBU859Iu6KrKniYsbHTRvluBBZd5 HYQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GJ0DCk1O6d5H3VZpNRGMlpZR8WwMvQ0AvTbFiTiGIgA=; b=e+sRb0mryp/FkwMl6dNeRzMZvlHv6ZifjyELBThTBavzuh1IlvX+vV15FJ+avNLfGF kR/pno9dFKPSvobvfoGv1LS6Ha7quFG0V6qK4cYGXmI+yj8VnfL8rcdvGYpBg/Djcvj+ ts4OknY/Sq/lm/QWfFMqhmYU3odI4eoETQ12/lx6+gnQrv5Lkmx5M3ssvhDO5W6qxhsG EyLn+M0GcU5GAgWGFze7XIeAS2WkPjSkbC0oYz9S3YF5icRquR7pR/Nh0mBuAzTl7PTt biUx+vD3Sk8vKsNafOGhWP8jzzhAfpcDPHbMhv2DZjXMOJHSVxoaOvVyFSds5OUw/eZa VyLQ== X-Gm-Message-State: ALoCoQlVTGByWO9OyW6u3t+3oJqU6DuNvT62xBUPRBAKuuUC8Kb5SwAg36+8QQmA9RPaBe8V3cNDiVf0l4+3KFLuyNctMLXHJQ== X-Received: by 10.194.209.195 with SMTP id mo3mr38087825wjc.16.1450101501325; Mon, 14 Dec 2015 05:58:21 -0800 (PST) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id w124sm6846546wmg.17.2015.12.14.05.58.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 Dec 2015 05:58:19 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v4 3/3] clk: qcom: Add A53 clock driver Date: Mon, 14 Dec 2015 15:58:03 +0200 Message-Id: <1450101483-23509-4-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450101483-23509-1-git-send-email-georgi.djakov@linaro.org> References: <1450101483-23509-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated A53 PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on platforms like MSM8916. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53cc.txt | 23 +++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53cc.c | 166 ++++++++++++++++++++ 4 files changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt create mode 100644 drivers/clk/qcom/a53cc.c -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt new file mode 100644 index 000000000000..3a1e8e6675ab --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt @@ -0,0 +1,23 @@ +Qualcomm A53 CPU Clock Controller Binding +------------------------------------------------ +The A53 CPU Clock Controller is hardware, which provides a combined +mux and divider functionality for the CPU clocks. It can choose between +a fixed rate clock and the dedicated A53 PLL. + +Required properties : +- compatible : shall contain: + + "qcom,a53cc" + +- reg : shall contain base register location and length + of the APCS region +- #clock-cells : shall contain 1 + +Example: + + apcs: syscon@b011000 { + compatible = "qcom,a53cc", "syscon"; + reg = <0x0b011000 0x1000>; + #clock-cells = <1>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d06cf687be4f..27a1622ca891 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -132,3 +132,11 @@ config QCOM_A53PLL support for CPU frequencies above 1GHz. Say Y if you want to support CPU frequency scaling on devices such as MSM8916. + +config QCOM_A53CC + bool "A53 Clock Controller" + depends on COMMON_CLK_QCOM && QCOM_A53PLL + help + Support for the A53 clock controller on some Qualcomm devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index bc7637516a6e..9a67697b9540 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,4 +26,5 @@ obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53CC) += a53cc.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53cc.c b/drivers/clk/qcom/a53cc.c new file mode 100644 index 000000000000..8958464ee7fb --- /dev/null +++ b/drivers/clk/qcom/a53cc.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +static const struct regmap_config a53cc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53cc_match_table[] = { + { .compatible = "qcom,a53cc" }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_a53cc_match_table); + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the a53 pll is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + + if (event == PRE_RATE_CHANGE) + ret = __mux_div_set_src_div(md, md->safe_src, md->safe_div); + + return notifier_from_errno(ret); +} + +static int qcom_a53cc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_regmap_mux_div *a53cc; + struct resource *res; + void __iomem *base; + struct clk *clk, *pclk; + struct regmap *regmap; + struct clk_init_data init; + int ret; + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + a53cc->reg_offset = 0x50, + a53cc->hid_width = 5, + a53cc->hid_shift = 0, + a53cc->src_width = 3, + a53cc->src_shift = 8, + a53cc->safe_src = 4, + a53cc->safe_div = 3, + a53cc->parent_map = gpll0_a53cc_map, + + init.name = "a53mux", + init.parent_names = gpll0_a53cc, + init.num_parents = 2, + init.ops = &clk_regmap_mux_div_ops, + init.flags = CLK_SET_RATE_PARENT; + a53cc->clkr.hw.init = &init; + + pclk = __clk_lookup(gpll0_a53cc[1]); + if (!pclk) + return -EPROBE_DEFER; + + ret = clk_prepare_enable(pclk); + if (ret) { + dev_err(dev, "failed to enable %s: %d\n", gpll0_a53cc[1], ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + regmap = devm_regmap_init_mmio(dev, base, &a53cc_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to init regmap mmio: %d\n", ret); + goto err; + } + + a53cc->clkr.regmap = regmap; + + clk = devm_clk_register_regmap(dev, &a53cc->clkr); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + return 0; +err: + clk_notifier_unregister(pclk, &a53cc->clk_nb); + return ret; +} + +static struct platform_driver qcom_a53cc_driver = { + .probe = qcom_a53cc_probe, + .driver = { + .name = "qcom-a53cc", + .of_match_table = qcom_a53cc_match_table, + }, +}; + +module_platform_driver(qcom_a53cc_driver); +MODULE_DESCRIPTION("Qualcomm A53 Clock Controller Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:qcom-a53cc");