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[199.106.103.254]) by mx.google.com with ESMTPSA id hv7sm11157144pdb.86.2015.04.17.16.49.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Apr 2015 16:49:26 -0700 (PDT) From: Lina Iyer To: arnd@arndb.de, catalin.marinas@arm.com, mark.rutland@arm.com, Will.Deacon@arm.com, lorenzo.pieralisi@arm.com Cc: daniel.lezcano@linaro.org, khilman@linaro.org, sboyd@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, msivasub@codeaurora.org, agross@codeaurora.org, mlocke@codeaurora.org, bryanh@codeaurora.org, Lina Iyer Subject: [PATCH RFC 3/7] qcom: spm: Use u32 for register offsets Date: Fri, 17 Apr 2015 17:49:05 -0600 Message-Id: <1429314549-6730-4-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1429314549-6730-1-git-send-email-lina.iyer@linaro.org> References: <1429314549-6730-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lina.iyer@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Newer SoC's allow a bigger memory range for the SPM. The offsets for the SPM sequences could therefore, be more than the capcacity of u8. Signed-off-by: Lina Iyer --- drivers/soc/qcom/spm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index b66d86c..392a714 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -60,7 +60,7 @@ enum spm_reg { }; struct spm_reg_data { - const u8 *reg_offset; + const u32 *reg_offset; u32 spm_cfg; u32 spm_dly; u32 pmic_dly; @@ -74,7 +74,7 @@ struct spm_driver_data { const struct spm_reg_data *reg_data; }; -static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { +static const u32 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, [SPM_REG_DLY] = 0x34, @@ -93,7 +93,7 @@ static const struct spm_reg_data spm_reg_8974_8084_cpu = { .start_index[PM_SLEEP_MODE_SPC] = 3, }; -static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { +static const u32 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24,