From patchwork Mon Oct 15 18:40:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 148881 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4134549lji; Mon, 15 Oct 2018 11:40:55 -0700 (PDT) X-Google-Smtp-Source: ACcGV60jAuHJ99LYAwcIg/cMbLCd7aXfoal12040InVuSbABp3pZ/U4xKylPepCa6MFFVKCySp4W X-Received: by 2002:a62:e80c:: with SMTP id c12-v6mr18869854pfi.124.1539628854890; Mon, 15 Oct 2018 11:40:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539628854; cv=none; d=google.com; s=arc-20160816; b=MH2m++YkuYa2zDhk4QELLLN/1f1srb4jh+fG7/Vn+jHtNd+Z4S8OC+22vTXEhtGOvs efR98/vsuDc+xc9VUwpz40t4eVBHI/j7kJ7tH3gdhcx8MsTDXDgog58lK611d9wcFXS6 OZbRE2rZobjYQPaexbPCB7xx1rHUBi8T0ayE8Onm1RncuQwHNLCZ9j+pqblQmZHTV3X7 1YidjENXnhKOQsBnbqI917sgV2Ph1m2Iho000xcmmbClimffgTggDy5kUs5wAa4qIY8h En0TftMkS184j/Dc6brmUzjCfknsBBdUZMGLZHygme/iWy9WHo9KvYt/oR/LfrBHxcpx hOvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=r+UnTmJ8JY3OzN0EBpE3/cD5XX1JGRK/5pblZ/iwIf1fTJOvqjz8rkIsvfD475bZx+ MPQ5uoHozcRa1jJHJVqBZMmsKl1nVD1lhj01dCDWrTOAF3bcSss+Kz9ILsO63hCtP7Ef XWwPqeernEg+ESQBaEOamhcjItxmKj+dRf5uedJaf/tB/BLZceJWef9IKH6JpWAWNe3k +sLW9FwvqktVumGImYUi8HQVixjAyhii9QhSmGWnzvR8ioI5+f7XwDGMQvmEgwWE87uA UhTQYF1xj9L5foh1oqdIrCeLUvb76fuqFqUato9244bIgthhKJMo4FUt2Yy3KlONqs4q 5Ajg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eG7AyAl4; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12-v6si10899735pll.105.2018.10.15.11.40.54; Mon, 15 Oct 2018 11:40:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eG7AyAl4; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726810AbeJPC1U (ORCPT + 13 others); Mon, 15 Oct 2018 22:27:20 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:43494 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726703AbeJPC1U (ORCPT ); Mon, 15 Oct 2018 22:27:20 -0400 Received: by mail-pl1-f196.google.com with SMTP id 30-v6so9710097plb.10 for ; Mon, 15 Oct 2018 11:40:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=eG7AyAl4mvM3K+g92MiM9uUWKlk4f3gpgxEDtc878UxFv09ypwwc7laEsEYU2dNAEx xLlbJyQp1Q2+pQNua5/b7I8ujrdOUVhXZ5u6dQ9WkIJA2oWFJRXpMTEFBeA2SYyk9si1 UB8+AryDuYy7sC0nUNIAOVvVCKI40LQCVR/OE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=atMP5jrDTSBoSL/c22ERDfmf0wccISIrwqr8zJ0RNJ+xVaLI/Y/W5y27eVVoxo75tz wjq/KVSU5V6tj+0g+NTbjF9yMROVW4Vi0BVOGNjIul4BT8ks/fjrcieZJXVGervQVxPm AlY8ZAgmjiUE9TNy+zXYBXXWGlxqj4e0CcdMY1u+CcUSpT89NUy70J11fPD41g8cLvBb icL7IItDD6CuA8/RYsF24C6PAu+nNZ0GGrYl3SF78fGbCT+F2QV1PrGrsv20a7LggH/G jHBNCwLAu11pBflr9NZUveXZkdUE8u5LRgTeh5d+kt3CGTbKw7gtsDYR0V6Dfq1iYP8L j5pw== X-Gm-Message-State: ABuFfoggBdtjdLE20hZVwBEX50oBcnv30oHBJeMLc2t0w+1KN0X/Fb3d mZyCKFaNyzl23IoquAijIAq+Yw== X-Received: by 2002:a17:902:a7:: with SMTP id a36-v6mr5207898pla.87.1539628853369; Mon, 15 Oct 2018 11:40:53 -0700 (PDT) Received: from localhost ([49.248.168.189]) by smtp.gmail.com with ESMTPSA id r73-v6sm18627774pfk.157.2018.10.15.11.40.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 11:40:52 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, Zhang Rui , Daniel Lezcano , Rob Herring , Mark Rutland Subject: [PATCH v1 1/4] dt: thermal: tsens: Add bindings for qcs404 Date: Tue, 16 Oct 2018 00:10:40 +0530 Message-Id: <102083e3ea93f48085b93f8df307967689ea18d6.1539627762.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 uses v1 of the TSENS IP block. Create a fallback DT property "qcom,tsens-v1" to gather common code. Signed-off-by: Amit Kucheria --- Documentation/devicetree/bindings/thermal/qcom-tsens.txt | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 1d9e8cf61018..799de3062352 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -8,9 +8,12 @@ Required properties: - "qcom,msm8996-tsens" (MSM8996) - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) + - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with version 2 of the TSENS IP. MSM8996 is the only exception because the generic property did not exist when support was added. + Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for + any SoC with version 1 of the TSENS IP. - reg: Address range of the thermal registers. New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM