| Message ID | 20250525-update_phy-v3-0-5b315cd39993@quicinc.com |
|---|---|
| Headers | show |
| Series | Update PCIe PHY settings for QCS8300 and SA8775P | expand |
On 5/25/25 3:29 PM, Dmitry Baryshkov wrote: > On Sun, May 25, 2025 at 11:27:18AM +0530, Mrinmay Sarkar wrote: >> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> >> >> The maximum link speed was previously restricted to Gen3 due to the >> absence of Gen4 equalization support in the driver. >> >> Add change to remove max link speed property, Since Gen4 equalization >> support has already been added into the driver. > > As Gen4 equalization is already supported by the XYZ driver remove the > max-link-speed property. > > "Add change to remove" is a bit clumsy. I'm more worried about this node not having these gen4 eq settings (i.e. the part talking about driver support landing is true, but it's unused without the presets being explicitly defined in eq-presets-16gts) Konrad
On 5/30/25 7:38 AM, Mrinmay Sarkar wrote: > On Tue, May 27, 2025 at 4:06 PM Konrad Dybcio > <konrad.dybcio@oss.qualcomm.com> wrote: >> >> On 5/25/25 3:29 PM, Dmitry Baryshkov wrote: >>> On Sun, May 25, 2025 at 11:27:18AM +0530, Mrinmay Sarkar wrote: >>>> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> >>>> >>>> The maximum link speed was previously restricted to Gen3 due to the >>>> absence of Gen4 equalization support in the driver. >>>> >>>> Add change to remove max link speed property, Since Gen4 equalization >>>> support has already been added into the driver. >>> >>> As Gen4 equalization is already supported by the XYZ driver remove the >>> max-link-speed property. >>> >>> "Add change to remove" is a bit clumsy. >> >> I'm more worried about this node not having these gen4 eq settings >> (i.e. the part talking about driver support landing is true, but it's >> unused without the presets being explicitly defined in eq-presets-16gts) >> >> Konrad > > Hi Konrad, > > Actually stability issue was resolved by this patch series: > https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org/ > and I don't think we need to define eq-presets-16gts for this. Okay, so there's multiple parts to it.. I was referring to this series https://lore.kernel.org/all/20250328-preset_v6-v9-0-22cfa0490518@oss.qualcomm.com/ Please check if you need this as well Konrad
On 5/30/25 12:50 PM, Konrad Dybcio wrote: > On 5/30/25 7:38 AM, Mrinmay Sarkar wrote: >> On Tue, May 27, 2025 at 4:06 PM Konrad Dybcio >> <konrad.dybcio@oss.qualcomm.com> wrote: >>> >>> On 5/25/25 3:29 PM, Dmitry Baryshkov wrote: >>>> On Sun, May 25, 2025 at 11:27:18AM +0530, Mrinmay Sarkar wrote: >>>>> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> >>>>> >>>>> The maximum link speed was previously restricted to Gen3 due to the >>>>> absence of Gen4 equalization support in the driver. >>>>> >>>>> Add change to remove max link speed property, Since Gen4 equalization >>>>> support has already been added into the driver. >>>> >>>> As Gen4 equalization is already supported by the XYZ driver remove the >>>> max-link-speed property. >>>> >>>> "Add change to remove" is a bit clumsy. >>> >>> I'm more worried about this node not having these gen4 eq settings >>> (i.e. the part talking about driver support landing is true, but it's >>> unused without the presets being explicitly defined in eq-presets-16gts) >>> >>> Konrad >> >> Hi Konrad, >> >> Actually stability issue was resolved by this patch series: >> https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org/ >> and I don't think we need to define eq-presets-16gts for this. > > Okay, so there's multiple parts to it.. > > I was referring to this series > > https://lore.kernel.org/all/20250328-preset_v6-v9-0-22cfa0490518@oss.qualcomm.com/ > > Please check if you need this as well If not, we can get this merged as-is Konrad
This Series is to update PCIe PHY settings as per latest hardware programming guide and remove max link speed dt property for SA8775P PCIe EP. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> --- V2 -> V3: - update subject in patch 1 as per review comment Link to v2: https://lore.kernel.org/r/20250514-update_phy-v2-0-d4f319221474@quicinc.com v1 -> v2: - Update commit message as per the review comments. - Remove max-link-speed DT property. --- Mrinmay Sarkar (2): phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 - drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 ++++++++++++---------- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 2 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h | 4 + .../phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v5.h | 11 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 6 files changed, 66 insertions(+), 43 deletions(-) --- base-commit: edef457004774e598fc4c1b7d1d4f0bcd9d0bb30 change-id: 20250513-update_phy-2cd804dd2401 Best regards,