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Tue, 29 Apr 2025 07:18:52 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 29 Apr 2025 00:18:52 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Shishkin CC: Mao Jinlong , , , , , Subject: [PATCH v2 0/2] Add Qualcomm extended CTI support Date: Tue, 29 Apr 2025 00:18:39 -0700 Message-ID: <20250429071841.1158315-1-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI5MDA1NCBTYWx0ZWRfXyM/5xamKtjF8 SguNJEMGCzP19PJyfsNEyTpPJQIlzmUVxR/6xu0/zqRNx7FaaW03hjB79K2dPcASB2Dbs6hokwA JOgxYmRsCoCLM557oTpw8C0z+Jov778IuKWKEvEt+Zzo/V4v40Tpcj3BdyNbjph5MjP9a6Ppqr2 23e7DaqTWsCOp311HKydV7MnZ0S1lWJ8BaJst4uVMDiamCBSezaDs5RnxrM1aCeKCSJR1xDUUtr jDjyNRRENhuODBu4NYrdOp1whhU0Q2r5HnR9MFfmgF9XKp/B1UNFrtyy+MDwtU0H/ohOHGRBv1d 7bjuBIh6yUlokxTR9dLiT6h2UgunDEBbhie2aQX7xqEUCZqY84a7KfMrzvurXur8cbZolEpXFNq 645cp4DRln8aJjGC1bddoMFC2n9p1D8WTTyVWXRWCr5O75Xe+ZiW/7MknCqarMBN+Bv/PQ+N X-Proofpoint-GUID: 4OFxk86Jss1NoNFQwer_mu8keip1_4FL X-Proofpoint-ORIG-GUID: 4OFxk86Jss1NoNFQwer_mu8keip1_4FL X-Authority-Analysis: v=2.4 cv=M/5NKzws c=1 sm=1 tr=0 ts=68107d5d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=3H110R4YSZwA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VDLssO2nRW9oqwq64HgA:9 a=NqO74GWdXPXpGKcKHaDJD/ajO6k=:19 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 bulkscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504290054 The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Changes in V2: 1. Add enum for compatible items. 2. Move offset arraies to coresight-cti-core Mao Jinlong (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 4 +- .../hwtracing/coresight/coresight-cti-core.c | 127 ++++++++++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 124 +++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 72 +++++----- 5 files changed, 243 insertions(+), 100 deletions(-)