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[0/4] arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling

Message ID 20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org
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Series arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling | expand

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Neil Armstrong Jan. 10, 2025, 3:21 p.m. UTC
Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (4):
      dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible
      arm64: dts: qcom: sm8650: add OSM L3 node
      arm64: dts: qcom: sm8650: add cpu interconnect nodes
      arm64: dts: qcom: add cpu OPP table with DDR, LLCC & L3 bandwidths

 .../bindings/interconnect/qcom,osm-l3.yaml         |   1 +
 arch/arm64/boot/dts/qcom/sm8650.dtsi               | 938 +++++++++++++++++++++
 2 files changed, 939 insertions(+)
---
base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246

Best regards,

Comments

Krzysztof Kozlowski Jan. 11, 2025, 10:53 a.m. UTC | #1
On Fri, Jan 10, 2025 at 04:21:18PM +0100, Neil Armstrong wrote:
> Document the OSM L3 found in the Qualcomm SM8650 platform.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof