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Thu, 28 Nov 2024 08:45:04 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 28 Nov 2024 00:45:01 -0800 From: Jingyi Wang Subject: [PATCH v3 0/4] Add initial support for QCS8300 SoC and QCS8300 RIDE board Date: Thu, 28 Nov 2024 16:44:42 +0800 Message-ID: <20241128-qcs8300_initial_dtsi-v3-0-26aa8a164914@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAHotSGcC/3XOTU4DMQwF4KuMsibI+WGSdMU9EKo8TkIt0Zk2C SNQ1buTTjcgwfI9y599ETUVTlXshosoaeXKy9yDeRgEHXB+S5Jjz0KDtkppL89UvQHY88yN8X0 fW2WJ0WQVDCUVneirp5Iyf27sy2vPB65tKV/blVXd2g2EAPZvcFUSZISEAXMkAPd8/mDimR5pO YobueofjH76h9GdscGShYwarf7NXO+vltTbyu3+r5iwJtnnR267IVs/kkdU4+SV03k0U4zkQKk RgXxw6LLJoDt2/QbUhTBUTQEAAA== To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: , , , , , Jingyi Wang , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs binding dependencies: - remoteproc: https://lore.kernel.org/linux-arm-msm/20240925-qcs8300_remoteproc_binding-v3-1-21b0c52b142b@quicinc.com/ - Reviewed - qfprom: https://lore.kernel.org/all/20240911-qcs8300_qfprom_binding-v2-1-d39226887493@quicinc.com/ - Reviewed - pdc: https://lore.kernel.org/all/20240911-qcs8300_binding-v2-1-de8641b3eaa1@quicinc.com/ - Reviewed Signed-off-by: Jingyi Wang --- Changes in v3: - Update title and cleanup signed-off-by tag(Bjorn) - fix the INTID of EL2 non-secure physical timer(Cong) - add reviewed-by tag(except for the dtsi patch for the code change) - code rebase - Link to v2: https://lore.kernel.org/r/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com Changes in v2: - decoupled from the original series - Drop compatible for QCS8275 - fix property order and add line breaks - move sleep_clk node to qcs8300-ride.dts - move l3-cache nodes out of l2-cache nodes and remove cluster1/cluster2 - add BWMON nodes - commit-msg update - Link to v1: https://lore.kernel.org/r/20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com --- Jingyi Wang (4): dt-bindings: arm: qcom: document QCS8300 SoC and reference board arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 arm64: dts: qcom: add QCS8300 platform arm64: dts: qcom: add base QCS8300 RIDE board Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 +++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1375 +++++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + 5 files changed, 1652 insertions(+), 1 deletion(-) --- base-commit: f486c8aa16b8172f63bddc70116a0c897a7f3f02 change-id: 20241128-qcs8300_initial_dtsi-ad3f193ce1d7 Best regards,