| Message ID | 20241128-qcs8300_initial_dtsi-v3-0-26aa8a164914@quicinc.com |
|---|---|
| Headers | show |
| Series | Add initial support for QCS8300 SoC and QCS8300 RIDE board | expand |
On Thu, Nov 28, 2024 at 04:44:44PM +0800, Jingyi Wang wrote: > Enable clock controller, interconnect and pinctrl for Qualcomm > QCS8300 platform to boot to UART console. ... which is used on the ABC DEF board. The defconfig is being enabled for everybody, so at least let them know which board increases the size of the default kernel build. > > The serial engine depends on gcc, interconnect and pinctrl. Since > the serial console driver is only available as built-in, so these > configs needs be built-in for the UART device to probe and register > the console. > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> > --- > arch/arm64/configs/defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index d13218d0c30f..3d9e48940c96 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -608,6 +608,7 @@ CONFIG_PINCTRL_MSM8996=y > CONFIG_PINCTRL_MSM8998=y > CONFIG_PINCTRL_QCM2290=y > CONFIG_PINCTRL_QCS404=y > +CONFIG_PINCTRL_QCS8300=y > CONFIG_PINCTRL_QDF2XXX=y > CONFIG_PINCTRL_QDU1000=y > CONFIG_PINCTRL_SA8775P=y > @@ -1327,6 +1328,7 @@ CONFIG_MSM_MMCC_8998=m > CONFIG_QCM_GCC_2290=y > CONFIG_QCM_DISPCC_2290=m > CONFIG_QCS_GCC_404=y > +CONFIG_QCS_GCC_8300=y > CONFIG_SC_CAMCC_7280=m > CONFIG_QDU_GCC_1000=y > CONFIG_SC_CAMCC_8280XP=m > @@ -1634,6 +1636,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y > CONFIG_INTERCONNECT_QCOM_OSM_L3=m > CONFIG_INTERCONNECT_QCOM_QCM2290=y > CONFIG_INTERCONNECT_QCOM_QCS404=m > +CONFIG_INTERCONNECT_QCOM_QCS8300=y > CONFIG_INTERCONNECT_QCOM_QDU1000=y > CONFIG_INTERCONNECT_QCOM_SA8775P=y > CONFIG_INTERCONNECT_QCOM_SC7180=y > > -- > 2.25.1 >
On Thu, Nov 28, 2024 at 04:44:46PM +0800, Jingyi Wang wrote: > Add initial support for Qualcomm QCS8300 RIDE board which enables DSPs, > UFS and booting to shell with uart console. > > Written with help from Tingguo Cheng (added rpmhpd nodes) and Xin Liu > (added ufs, adsp and gpdsp nodes). > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 2 +- > arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 ++++++++++++++++++++++++++++++ > 2 files changed, 268 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 9bb8b191aeb5..d9545743606a 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -114,7 +114,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb > -dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb > +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb It would be good to add a comment to the commit message about why you are removing qcs8550-aim300-aiot.dtb from the Makefile. Andrew
On 28/11/2024 17:49, Andrew Lunn wrote: > On Thu, Nov 28, 2024 at 04:44:46PM +0800, Jingyi Wang wrote: >> Add initial support for Qualcomm QCS8300 RIDE board which enables DSPs, >> UFS and booting to shell with uart console. >> >> Written with help from Tingguo Cheng (added rpmhpd nodes) and Xin Liu >> (added ufs, adsp and gpdsp nodes). >> >> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 2 +- >> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 ++++++++++++++++++++++++++++++ >> 2 files changed, 268 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index 9bb8b191aeb5..d9545743606a 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -114,7 +114,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb >> -dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb > > It would be good to add a comment to the commit message about why you > are removing qcs8550-aim300-aiot.dtb from the Makefile. Especially that it was not in v2 (which I reviewed) and nothing in the changelog explains this removal. Best regards, Krzysztof
On 11/29/2024 1:40 AM, Krzysztof Kozlowski wrote: > On 28/11/2024 17:49, Andrew Lunn wrote: >> On Thu, Nov 28, 2024 at 04:44:46PM +0800, Jingyi Wang wrote: >>> Add initial support for Qualcomm QCS8300 RIDE board which enables DSPs, >>> UFS and booting to shell with uart console. >>> >>> Written with help from Tingguo Cheng (added rpmhpd nodes) and Xin Liu >>> (added ufs, adsp and gpdsp nodes). >>> >>> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> >>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 2 +- >>> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 ++++++++++++++++++++++++++++++ >>> 2 files changed, 268 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index 9bb8b191aeb5..d9545743606a 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -114,7 +114,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb >>> -dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb >> >> It would be good to add a comment to the commit message about why you >> are removing qcs8550-aim300-aiot.dtb from the Makefile. > > Especially that it was not in v2 (which I reviewed) and nothing in the > changelog explains this removal. > sorry it was a typo, will fix that > Best regards, > Krzysztof
On 11/29/2024 12:49 AM, Andrew Lunn wrote: > On Thu, Nov 28, 2024 at 04:44:46PM +0800, Jingyi Wang wrote: >> Add initial support for Qualcomm QCS8300 RIDE board which enables DSPs, >> UFS and booting to shell with uart console. >> >> Written with help from Tingguo Cheng (added rpmhpd nodes) and Xin Liu >> (added ufs, adsp and gpdsp nodes). >> >> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 2 +- >> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 ++++++++++++++++++++++++++++++ >> 2 files changed, 268 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index 9bb8b191aeb5..d9545743606a 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -114,7 +114,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb >> -dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb > > It would be good to add a comment to the commit message about why you > are removing qcs8550-aim300-aiot.dtb from the Makefile. > > Andrew sorry it was a typo, will fix that Thanks, Jingyi
On 11/28/2024 9:12 PM, Dmitry Baryshkov wrote: > On Thu, Nov 28, 2024 at 04:44:44PM +0800, Jingyi Wang wrote: >> Enable clock controller, interconnect and pinctrl for Qualcomm >> QCS8300 platform to boot to UART console. > > ... which is used on the ABC DEF board. The defconfig is being enabled > for everybody, so at least let them know which board increases the size > of the default kernel build. > will add that >> >> The serial engine depends on gcc, interconnect and pinctrl. Since >> the serial console driver is only available as built-in, so these >> configs needs be built-in for the UART device to probe and register >> the console. >> >> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >> --- >> arch/arm64/configs/defconfig | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index d13218d0c30f..3d9e48940c96 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -608,6 +608,7 @@ CONFIG_PINCTRL_MSM8996=y >> CONFIG_PINCTRL_MSM8998=y >> CONFIG_PINCTRL_QCM2290=y >> CONFIG_PINCTRL_QCS404=y >> +CONFIG_PINCTRL_QCS8300=y >> CONFIG_PINCTRL_QDF2XXX=y >> CONFIG_PINCTRL_QDU1000=y >> CONFIG_PINCTRL_SA8775P=y >> @@ -1327,6 +1328,7 @@ CONFIG_MSM_MMCC_8998=m >> CONFIG_QCM_GCC_2290=y >> CONFIG_QCM_DISPCC_2290=m >> CONFIG_QCS_GCC_404=y >> +CONFIG_QCS_GCC_8300=y >> CONFIG_SC_CAMCC_7280=m >> CONFIG_QDU_GCC_1000=y >> CONFIG_SC_CAMCC_8280XP=m >> @@ -1634,6 +1636,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >> CONFIG_INTERCONNECT_QCOM_QCM2290=y >> CONFIG_INTERCONNECT_QCOM_QCS404=m >> +CONFIG_INTERCONNECT_QCOM_QCS8300=y >> CONFIG_INTERCONNECT_QCOM_QDU1000=y >> CONFIG_INTERCONNECT_QCOM_SA8775P=y >> CONFIG_INTERCONNECT_QCOM_SC7180=y >> >> -- >> 2.25.1 >> > Thanks, Jingyi
On 11/28/2024 9:29 PM, Dmitry Baryshkov wrote: >> +#include "qcs8300.dtsi" >> +/ { >> + model = "Qualcomm Technologies, Inc. QCS8300 Ride"; >> + compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; >> + chassis-type = "embedded"; >> + >> + aliases { >> + serial0 = &uart7; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + clocks { >> + xo_board_clk: xo-board-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <38400000>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <32000>; >> + }; > Move both clocks to the qcs8300.dtsi. If you wish, you can keep > frequencies in the board DT file. > Dmirty, Move xo clock and sleep clock to board DT from SoC DT are due to review comments in [1] and [2]. As you and Krzysztof discussed in [3], there're pros and cons for different solutions. There are three possible ways. Put these two clocks in board DT is aligned with hardware. These two clocks are provided by PMIC instead of SoC. Put these two clocks in SoC DT can reduce duplication since they are not supposed to be changed on different board. Put these two clocks in SoC DT and set frequency in board DT. We need a unify way to deal with this kind of nodes and keep it consistent across Qualcomm SoC. Who shall make this decision? [1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/ [2]https://lore.kernel.org/all/be8b573c-db4e-4eec-a9a6-3cd83d04156d@kernel.org/ [3]https://lore.kernel.org/all/4kopdkvbkrpcpzwteezm427ml5putqvzsnfkpmg76spsple7l5@mg7v3ihwxnit/ >> + }; >> +}; >> +
On Fri, Nov 29, 2024 at 11:13:28AM +0800, Tingwei Zhang wrote: > On 11/28/2024 9:29 PM, Dmitry Baryshkov wrote: > > > +#include "qcs8300.dtsi" > > > +/ { > > > + model = "Qualcomm Technologies, Inc. QCS8300 Ride"; > > > + compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; > > > + chassis-type = "embedded"; > > > + > > > + aliases { > > > + serial0 = &uart7; > > > + }; > > > + > > > + chosen { > > > + stdout-path = "serial0:115200n8"; > > > + }; > > > + > > > + clocks { > > > + xo_board_clk: xo-board-clk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <38400000>; > > > + }; > > > + > > > + sleep_clk: sleep-clk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <32000>; > > > + }; > > Move both clocks to the qcs8300.dtsi. If you wish, you can keep > > frequencies in the board DT file. > > > Dmirty, > > Move xo clock and sleep clock to board DT from SoC DT are due to review > comments in [1] and [2]. > > As you and Krzysztof discussed in [3], there're pros and cons for different > solutions. There are three possible ways. > > Put these two clocks in board DT is aligned with hardware. These two clocks > are provided by PMIC instead of SoC. > > Put these two clocks in SoC DT can reduce duplication since they are not > supposed to be changed on different board. > > Put these two clocks in SoC DT and set frequency in board DT. > > We need a unify way to deal with this kind of nodes and keep it consistent > across Qualcomm SoC. > > Who shall make this decision? After an offline discussion I've send [4]. [4] https://lore.kernel.org/linux-arm-msm/20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org/ > > [1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/ > [2]https://lore.kernel.org/all/be8b573c-db4e-4eec-a9a6-3cd83d04156d@kernel.org/ > [3]https://lore.kernel.org/all/4kopdkvbkrpcpzwteezm427ml5putqvzsnfkpmg76spsple7l5@mg7v3ihwxnit/ > > > > + }; > > > +}; > > > + > > > -- > Thanks, > Tingwei
Introduce the Device Tree for the QCS8300 platform. Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs binding dependencies: - remoteproc: https://lore.kernel.org/linux-arm-msm/20240925-qcs8300_remoteproc_binding-v3-1-21b0c52b142b@quicinc.com/ - Reviewed - qfprom: https://lore.kernel.org/all/20240911-qcs8300_qfprom_binding-v2-1-d39226887493@quicinc.com/ - Reviewed - pdc: https://lore.kernel.org/all/20240911-qcs8300_binding-v2-1-de8641b3eaa1@quicinc.com/ - Reviewed Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> --- Changes in v3: - Update title and cleanup signed-off-by tag(Bjorn) - fix the INTID of EL2 non-secure physical timer(Cong) - add reviewed-by tag(except for the dtsi patch for the code change) - code rebase - Link to v2: https://lore.kernel.org/r/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com Changes in v2: - decoupled from the original series - Drop compatible for QCS8275 - fix property order and add line breaks - move sleep_clk node to qcs8300-ride.dts - move l3-cache nodes out of l2-cache nodes and remove cluster1/cluster2 - add BWMON nodes - commit-msg update - Link to v1: https://lore.kernel.org/r/20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com --- Jingyi Wang (4): dt-bindings: arm: qcom: document QCS8300 SoC and reference board arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 arm64: dts: qcom: add QCS8300 platform arm64: dts: qcom: add base QCS8300 RIDE board Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 +++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1375 +++++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + 5 files changed, 1652 insertions(+), 1 deletion(-) --- base-commit: f486c8aa16b8172f63bddc70116a0c897a7f3f02 change-id: 20241128-qcs8300_initial_dtsi-ad3f193ce1d7 Best regards,