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Mon, 18 Nov 2024 08:26:24 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4AI8QN0V010282; Mon, 18 Nov 2024 08:26:23 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4AI8QNEt010281 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Nov 2024 08:26:23 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id DB8DF176D; Mon, 18 Nov 2024 16:26:21 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, kw@linux.com, lpieralisi@kernel.org, quic_qianyu@quicinc.com, conor+dt@kernel.org, neil.armstrong@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Ziyue Zhang , Krishna chaitanya chundru Subject: [PATCH 0/5] pci: qcom: Add QCS615 PCIe support Date: Mon, 18 Nov 2024 16:26:14 +0800 Message-Id: <20241118082619.177201-1-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ea1OId-dyM6fcow3BHCb8OonsayJLODm X-Proofpoint-GUID: Ea1OId-dyM6fcow3BHCb8OonsayJLODm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxlogscore=732 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 mlxscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411180070 Update the relavent DT bindings for PCIe, add new config to the phy driver add pcie and phy nodes to the .dtsi file and enable then in board .dts file for the qcs615-ride platform. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- Have folling changes: - Add compatible and phy compatible for qcs615 platform. - Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. - Add a new Document the QCS615 PCIe Controller - Add the compatible for QCS615 PCIe controller. - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Krishna chaitanya chundru (5): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS615 QMP PCIe PHY Gen3 x1 phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe dt-bindings: PCI: qcom: Document the QCS615 PCIe Controller PCI: qcom: Add QCS615 PCIe support arm64: dts: qcom: qcs615: enable pcie for qcs615 .../bindings/pci/qcom,pcie-qcs615.yaml | 161 ++++++++++++++++++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 +++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 158 +++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 ++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 + 7 files changed, 470 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml base-commit: 075857dab69e8d673eeaa4aa7f5228796a4c010d