From patchwork Tue Nov 12 17:30:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 842761 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2FCD213EE0; Tue, 12 Nov 2024 17:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731432685; cv=none; b=AxtdCa7ErzB5IL0Kjs5y/S/yZkGIMxcczASQmsxIyqZ5K8WqfPg2nT/12F7ve7FutHBQzOLtxGRDMXhZQysQnsHcvJzmwoyBC/CgQHuXeQK/D/q18LTYz4roM1sfgCdS+0UOCm0tzPiVP3Vvbhq7gV1hMnuZ+kxyZOOjTgGgyu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731432685; c=relaxed/simple; bh=yE7UikHJy+hBeOLefH+rwzRBvRVZMVmKoI8WK8RAra8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=hNlzPEcJkqmb71cuYmGK62+49AzKhMCq3QTjKoLBZ/J6OhZQLJpehqNP8kDh8ebS2L1iNYO6YQ4YP/xHxSEWs6kDMvcQ6jr4Iqra5mCZZCM7kwuBdenxtsgUmYjnFlbMBumNxFt/UchrU8oQE0c/9c/lzLq3Q72NKO0kJZYi9ZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=L/qZX0fT; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="L/qZX0fT" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ACFm1ZF004274; Tue, 12 Nov 2024 17:31:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=MjjEodL9bCqEtWU+oD6Erk vAc5jOc0Aews3a/DgXGKI=; b=L/qZX0fTBe/Z0R6xVNPZAmj19DRIbkrBW/vTKi e0FETM+IO2qGDmya4DiiV+4tWPaLwq5quBsu6chEaycHzMh8gjII7k7nmYVofJSb ModuSdxxM19zq75AnPP2h7N4zWsJgKyENtxZOw2Gc2RycyJhQVkw7cHlev4NdzTq yGWZj8AKz/KBlG5Z6VPiud+JGdpI1rUQhNmZlgNK6ID5g3QTSM5Kkfkwp10p91vT kiohgVSTG4yvmzzhdwGp+5J0uFkJjqoc0MhrUkvMtv32CrsqJeXL7LIAWWZGEN40 OGNQ1c6qMiEciccKNfuiCG3tJP2zYi2eopP1nFcPkZzjfZqQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42v1h6huvf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 17:31:10 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ACHVAeq010331 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 17:31:10 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 12 Nov 2024 09:31:01 -0800 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v5 0/5] media: qcom: camss: Add sc7280 support Date: Tue, 12 Nov 2024 23:00:27 +0530 Message-ID: <20241112173032.2740119-1-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BpYUkPYKyUyXcdXpbHFSU0-K756sVLKo X-Proofpoint-GUID: BpYUkPYKyUyXcdXpbHFSU0-K756sVLKo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411120140 SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY, CSID, VFE/RDI interfaces in SC7280. SC7280 provides - 3 x VFE, 3 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE - 3 x CSID - 2 x CSID Lite - 5 x CSI PHY The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine the base dts for qcs6490-rb3gen2 is: https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/ This change is dependent on below series. As it is raised on top of this. Please take both to validate. This change was raised as [PATCH v4 4/6] in V4 of this series. https://lore.kernel.org/linux-arm-msm/20241112133846.2397017-2-quic_vikramsa@quicinc.com/ Changes in V5: - Updated Commit text for [PATCH v5 1/6]. - Moved reg after compatible string. - Renamed csi'x' clocks to vfe'x'_csid - Removed [PATCH v4 4/6] and raised a seprate series for this one. - Moved gpio states to mezzanine dtso. - Added more clock levels to address TPG related issues. - Renamed power-domains-names -> power-domain-names. - Link to v4: https://lore.kernel.org/linux-arm-msm/20241030105347.2117034-1-quic_vikramsa@quicinc.com/ Changes in V4: - V3 had 8 patches and V4 is reduced to 6. - Removed [Patch v3 2/8] as binding change is not required for dtso. - Removed [Patch v3 3/8] as the fix is already taken care in latest kernel tip. - Updated alignment for dtsi and dt-bindings. - Adding qcs6490-rb3gen2-vision-mezzanine as overlay. - Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/ Changes in V3: - Added missed subject line for cover letter of V2. - Updated Alignment, indentation and properties order. - edit commit text for [PATCH 02/10] and [PATCH 03/10]. - Refactor camss_link_entities. - Removed camcc enablement changes as it already done. - Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/ Changes in V2: - Improved indentation/formatting. - Removed _src clocks and misleading code comments. - Added name fields for power domains and csid register offset in DTSI. - Dropped minItems field from YAML file. - Listed changes in alphabetical order. - Updated description and commit text to reflect changes - Changed the compatible string from imx412 to imx577. - Added board-specific enablement changes in the newly created vision board DTSI file. - Fixed bug encountered during testing. - Moved logically independent changes to a new/seprate patch. - Removed cci0 as no sensor is on this port and MCLK2, which was a copy-paste error from the RB5 board reference. - Added power rails, referencing the RB5 board. - Discarded Patch 5/6 completely (not required). - Removed unused enums. - Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/ Suresh Vankadara (1): media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma (4): media: dt-bindings: Add qcom,sc7280-camss media: qcom: camss: Sort camss version enums and compatible strings arm64: dts: qcom: sc7280: Add support for camss arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine .../bindings/media/qcom,sc7280-camss.yaml | 415 ++++++++++++++++++ arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcs6490-rb3gen2-vision-mezzanine.dtso | 108 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 170 +++++++ .../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +- .../media/platform/qcom/camss/camss-csiphy.c | 5 + .../media/platform/qcom/camss/camss-csiphy.h | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 8 +- drivers/media/platform/qcom/camss/camss.c | 311 ++++++++++++- drivers/media/platform/qcom/camss/camss.h | 5 +- 10 files changed, 1030 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso