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Fri, 8 Nov 2024 04:09:41 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 20:09:35 -0800 From: Taniya Das Subject: [PATCH v3 00/11] Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform Date: Fri, 8 Nov 2024 09:39:17 +0530 Message-ID: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAO6OLWcC/33OQQ6CMBAF0KuQrq1pEYu48h7GRR0GmQittNhoC He3oMa4Yfl/Mu/PwDw6Qs/2ycAcBvJkTQybVcKg1uaCnMqYWSrSTAqpeAdeyS1vWw6NhStY0zv bNOg4VFWhUedaCMXi/c1hRY/ZPp5irsn31j3nqSCn9qsWC2qQXPAMqnOhyjyPA4fuTkAG1mBbN rkh/VkRW7LSaJVSZ7tc6Exj+W+N76cdxtZT//l8HF/qaQ4uJQEAAA== X-Change-ID: 20241016-qcs615-mm-clockcontroller-cff9aea7a006 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Dmitry Baryshkov , Gabor Juhos , Krzysztof Kozlowski , Bryan O'Donoghue X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XkFmLv-7ZCJ_dxIMkn5bv04_h9ehDhEi X-Proofpoint-ORIG-GUID: XkFmLv-7ZCJ_dxIMkn5bv04_h9ehDhEi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411080034 Add support for multimedia clock controllers on Qualcomm QCS615 platform. Update the defconfig to enable these clock controllers. Global clock controller support https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com/ Signed-off-by: Taniya Das --- Changes in v3: - update PLL configs to use BIT and GENMASK for vco_val and vco_mask for all CCs [Bryan O'Donoghue] - Link to v2: https://lore.kernel.org/r/20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com Changes in v2: - cleanups in clk_alpha_pll_slew_update and clk_alpha_pll_slew_enable functions [Christophe] - update PLL configs for "vco_val = 0x0" shift(20) [Bryan O'Donoghue] - update PLL configs to use lower case for L value [Dmitry] - Link parents for IFE/IPE/BPS GDSCs as Titan Top GDSC [Bryan O'Donoghue, Dmitry] - Remove DT_BI_TCXO_AO from camcc-qcs615 [Dmitry] - Remove HW_CTRL_TRIGGER from camcc-qcs615 [Bryan O'Donoghue] - Update platform name for default configuration [Dmitry] - Link to v1: https://lore.kernel.org/r/20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com --- Taniya Das (11): clk: qcom: Update the support for alpha mode configuration clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Display clock controller clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Video clock controller clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver arm64: defconfig: Enable QCS615 clock controllers .../bindings/clock/qcom,qcs615-camcc.yaml | 60 + .../bindings/clock/qcom,qcs615-dispcc.yaml | 73 + .../bindings/clock/qcom,qcs615-gpucc.yaml | 66 + .../bindings/clock/qcom,qcs615-videocc.yaml | 64 + arch/arm64/configs/defconfig | 4 + drivers/clk/qcom/Kconfig | 35 + drivers/clk/qcom/Makefile | 4 + drivers/clk/qcom/camcc-qcs615.c | 1591 ++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 172 +++ drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/dispcc-qcs615.c | 786 ++++++++++ drivers/clk/qcom/gpucc-qcs615.c | 525 +++++++ drivers/clk/qcom/videocc-qcs615.c | 332 ++++ include/dt-bindings/clock/qcom,qcs615-camcc.h | 110 ++ include/dt-bindings/clock/qcom,qcs615-dispcc.h | 52 + include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 + include/dt-bindings/clock/qcom,qcs615-videocc.h | 30 + 17 files changed, 3944 insertions(+) --- base-commit: 15e7d45e786a62a211dd0098fee7c57f84f8c681 change-id: 20241016-qcs615-mm-clockcontroller-cff9aea7a006 Best regards,