| Message ID | 20241021-gpu-acd-v2-0-9c25a62803bc@quicinc.com |
|---|---|
| Headers | show |
| Series | Support for GPU ACD feature on Adreno X1-85 | expand |
On 21/10/2024 12:53, Akhil P Oommen wrote: > ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce > the power consumption. In some chipsets, it is also a requirement to > support higher GPU frequencies. This patch adds support for GPU ACD by > sending necessary data to GMU and AOSS. The feature support for the > chipset is detected based on devicetree data. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 81 ++++++++++++++++++++++++++++------- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 ++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++++++ > 4 files changed, 124 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 37927bdd6fbe..09fb3f397dbb 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -1021,14 +1021,6 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) > > gmu->hung = false; > > - /* Notify AOSS about the ACD state (unimplemented for now => disable it) */ > - if (!IS_ERR(gmu->qmp)) { > - ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", > - 0 /* Hardcode ACD to be disabled for now */); > - if (ret) > - dev_err(gmu->dev, "failed to send GPU ACD state\n"); > - } > - > /* Turn on the resources */ > pm_runtime_get_sync(gmu->dev); > > @@ -1476,6 +1468,64 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) > return a6xx_gmu_rpmh_votes_init(gmu); > } > > +static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) > +{ > + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > + struct a6xx_hfi_acd_table *cmd = &gmu->acd_table; > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > + struct msm_gpu *gpu = &adreno_gpu->base; > + int ret, i, cmd_idx = 0; > + > + cmd->version = 1; > + cmd->stride = 1; > + cmd->enable_by_level = 0; > + > + /* Skip freq = 0 and parse acd-level for rest of the OPPs */ > + for (i = 1; i < gmu->nr_gpu_freqs; i++) { > + struct dev_pm_opp *opp; > + struct device_node *np; > + unsigned long freq; > + u32 val; > + > + freq = gmu->gpu_freqs[i]; > + opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); > + np = dev_pm_opp_get_of_node(opp); > + > + ret = of_property_read_u32(np, "qcom,opp-acd-level", &val); > + of_node_put(np); > + dev_pm_opp_put(opp); > + if (ret == -EINVAL) > + continue; > + else if (ret) { > + DRM_DEV_ERROR(gmu->dev, "Unable to read acd level for freq %lu\n", freq); > + return ret; > + } > + > + cmd->enable_by_level |= BIT(i); > + cmd->data[cmd_idx++] = val; How do you know that cmd_idx is always < sizeof(cmd->data); ? > + } > + > + cmd->num_levels = cmd_idx; > + > + /* We are done here if ACD is not required for any of the OPPs */ > + if (!cmd->enable_by_level) > + return 0; > + > + /* Initialize qmp node to talk to AOSS */ > + gmu->qmp = qmp_get(gmu->dev); > + if (IS_ERR(gmu->qmp)) { > + cmd->enable_by_level = 0; > + return dev_err_probe(gmu->dev, PTR_ERR(gmu->qmp), "Failed to initialize qmp\n"); > + } > + > + /* Notify AOSS about the ACD state */ > + ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", 1); > + if (ret) > + DRM_DEV_ERROR(gmu->dev, "failed to send GPU ACD state\n"); > + > + return 0; Shouldn't the ret from gmp_send() get propogated in the return of this function ? i.e. how can your probe be successful if the notification failed ? --- bod
This series adds support for ACD feature for Adreno GPU which helps to lower the power consumption on GX rail and also sometimes is a requirement to enable higher GPU frequencies. At high level, following are the sequences required for ACD feature: 1. Identify the ACD level data for each regulator corner 2. Send a message to AOSS to switch voltage plan 3. Send a table with ACD level information to GMU during every gpu wake up For (1), it is better to keep ACD level data in devicetree because this value depends on the process node, voltage margins etc which are chipset specific. For instance, same GPU HW IP on a different chipset would have a different set of values. So, a new schema which extends opp-v2 is created to add a new property called "qcom,opp-acd-level". ACD support is dynamically detected based on the presence of "qcom,opp-acd-level" property in GPU's opp table. Also, qmp node should be present under GMU node in devicetree for communication with AOSS. The devicetree patch in this series adds the acd-level data for X1-85 GPU present in Snapdragon X1 Elite chipset. This series is rebased on top of drm-msm/msm-next. --- Changes in v2: - Removed RFC tag for the series - Improve documentation for the new dt bindings (Krzysztof) - Add fallback compatible string for opp-table (Krzysztof) - Link to v1: https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com --- Akhil P Oommen (3): drm/msm/adreno: Add support for ACD dt-bindings: opp: Add v2-qcom-adreno vendor bindings arm64: dts: qcom: x1e80100: Add ACD levels for GPU .../bindings/opp/opp-v2-qcom-adreno.yaml | 96 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 81 ++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 ++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++ 6 files changed, 230 insertions(+), 16 deletions(-) --- base-commit: a20a91fb1bfac5d05ec5bcf9afe0c9363f6c8c93 change-id: 20240724-gpu-acd-6c1dc5dcf516 Best regards,