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[46.53.210.75]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a9937615e85sm367362266b.175.2024.10.07.08.36.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 08:36:14 -0700 (PDT) From: Dzmitry Sankouski Subject: [PATCH v6 0/2] Add divisor computation feature for sdm845 gp clocks Date: Mon, 07 Oct 2024 18:36:10 +0300 Message-Id: <20241007-starqltechn_integration_upstream-v6-0-dd75c06c708d@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOr/A2cC/43QTWrDMBAF4KsErasiS9ZPuuo9SghjeWwLbDmVF JESfPdOAqWhm2b5Bul7w1xZxhQws7fdlSWsIYc1UjAvO+YniCPy0FNmUshWmMbyXCB9zgX9FI8 hFhwTFPpzPJ9ySQgL77wzTotODqgYMR1k5F2C6CeC4nmeaXhKOITLvffjQHkKuazp675GVbfpT 6P7v7EqLjiqwRgjRWPBv48LhPnVrwu74bX9BfeNegJsCZS9xKHXXjtr/4L6ccMnblI1gZae7jW CFq59BLdt+wYvFpamhwEAAA== To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dzmitry Sankouski X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728315373; l=2459; i=dsankouski@gmail.com; s=20240619; h=from:subject:message-id; bh=O5hxrvpff939xBpLOlRIOWFF+GV6E6GhdFtYVQrksos=; b=QqcJ5RtqAjBM5Z5mLzGvHXhr1iTqJUKKvIuaTSZKeXYnT4IH+SEylsXY87B/+2TgwkC2lEv0i LPyjw0YblazBHu1moBAh8E7EsbPR9xBa9o+YuxXLYSymcV8VR4mjowZ X-Developer-Key: i=dsankouski@gmail.com; a=ed25519; pk=YJcXFcN1EWrzBYuiE2yi5Mn6WLn6L1H71J+f7X8fMag= SDM845 has "General Purpose" clocks that can be muxed to SoC pins to clock various external devices. Those clocks may be used as e.g. PWM sources for external peripherals. GPCLK can in theory have arbitrary value depending on the use case, so the concept of frequency tables, used in rcg2 clock driver, is not efficient, because it allows only defined frequencies. Introduce clk_rcg2_gp_ops, which automatically calculate clock mnd values for arbitrary clock rate. The calculation done as follows: - upon determine rate request, we calculate m/n/pre_div as follows: - find parent(from our client's assigned-clock-parent) rate - find scaled rates by dividing rates on its greatest common divisor - assign requested scaled rate to m - factorize scaled parent rate, put multipliers to n till max value (determined by mnd_width) - validate calculated values with *_width: - if doesn't fit, delete divisor and multiplier by 2 until fit - return determined rate Limitations: - The driver doesn't select a parent clock (it may be selected by client in device tree with assigned-clocks, assigned-clock-parents properties) Signed-off-by: Dzmitry Sankouski --- Changes in v6: - fix kernel robot issues - run sparse and smatch - Link to v5: https://lore.kernel.org/r/20240617-starqltechn_integration_upstream-v5-0-761795ea5084@gmail.com Changes in v5: - Split patchset per subsystem - Link to v4: https://lore.kernel.org/r/20240913-starqltechn_integration_upstream-v4-0-2d2efd5c5877@gmail.com Changes in v4: - Replace gcc-845 freq_tbl frequencies patch with new approach, based on automatic m/n/pre_div value generation - Link to v3: https://lore.kernel.org/r/20240618-starqltechn_integration_upstream-v3-0-e3f6662017ac@gmail.com --- Dzmitry Sankouski (2): clk: qcom: clk-rcg2: document calc_rate function gcc-sdm845: Add general purpose clock ops drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 200 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----- drivers/clk/qcom/gcc-sdm845.c | 11 ++------ 3 files changed, 197 insertions(+), 15 deletions(-) --- base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75 change-id: 20240617-starqltechn_integration_upstream-bc86850b2fe3 Best regards,