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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd5e333sm259724e87.76.2024.09.27.03.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:32:14 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Jagadeesh Kona Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 0/3] arm: qcom: sm8550: Change camcc power domain from MMCX to MXC Date: Fri, 27 Sep 2024 13:32:09 +0300 Message-ID: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The problem is trivial to reproduce and the fix is trivial to verify, it's sufficient to enable SM8550 camera clock controller and a CCI controller, for instance on SM8550-QRD CCI0 or CCI1 can be enabled: &cci0 { status = "okay"; }; I made a special effort to check that the power domain in SM8550 camcc is sufficient to be replaced, and Titan and other provided GDSCs can be turned on/off, if the clock controller is disconneced from MMCX and MMCX is off according to /sys/kernel/debug/pm_genpd/pm_genpd_summary. Vladimir Zapolskiy (3): arm64: dts: qcom: sm8550: Change camcc power domain from MMCX to MXC dt-bindings: clock: qcom,sm8450-camcc: do not restrict power domain to MMCX dt-bindings: clock: qcom,sm8450-camcc: generalize title and description .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) base-commit: 11a299a7933e03c83818b431e6a1c53ad387423d