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[0/4] drm/msm/mdss: rework UBWC registers programming

Message ID 20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org
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Series drm/msm/mdss: rework UBWC registers programming | expand

Message

Dmitry Baryshkov Sept. 21, 2024, 8:17 a.m. UTC 
Current way of programming of the UBWC-related registers has been
inherited from vendor's drivers. The ubwc_static was supposed to contain
raw data to be programmed to the hardware, but was later repurposed to
define of the bits. As it can be seen by the commit 3e30296b374a
("drm/msm: fix the highest_bank_bit for sc7180") sometimes this data
gets out of sync.

Rework existing msm_mdss_setup_ubwc_dec_NN() functions to be closer to
the actual hardware bit definitions. Drop the ubwc_static field.

Unfortunately this also introduces several "unknown" bits, for which we
do not document the actual purpose. Hopefully comparing this data with
the more documented Adreno UBWC feature bits will provide information
about the meaning of those bits.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dmitry Baryshkov (4):
      drm/msm: move MDSS registers to separate header file
      drm/msm/mdss: use register definitions instead of hand-coding them
      drm/msm/mdss: define bitfields for the UBWC_STATIC register
      drm/msm/mdss: reuse defined bitfields for UBWC 2.0

 drivers/gpu/drm/msm/Makefile                   |  1 +
 drivers/gpu/drm/msm/msm_mdss.c                 | 86 ++++++++++++++------------
 drivers/gpu/drm/msm/msm_mdss.h                 |  4 +-
 drivers/gpu/drm/msm/registers/display/mdp5.xml | 16 -----
 drivers/gpu/drm/msm/registers/display/mdss.xml | 38 ++++++++++++
 5 files changed, 89 insertions(+), 56 deletions(-)
---
base-commit: 32ffa5373540a8d1c06619f52d019c6cdc948bb4
change-id: 20240921-msm-mdss-ubwc-105589e05f35

Best regards,