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Tue, 27 Aug 2024 12:46:15 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 27 Aug 2024 05:46:10 -0700 From: Luo Jie Subject: [PATCH v3 0/4] Add CMN PLL clock controller driver for IPQ9574 Date: Tue, 27 Aug 2024 20:45:58 +0800 Message-ID: <20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAIbKzWYC/3XNwQ6CMAyA4VchPTvTbSLTk+9hDJFtSBMYsOmiI by7g5PGePyb9usEwXqyAY7ZBN5GCtS7FHKTgW6u7mYZmdQgUOxQoWKj7ruShrHUnRvalhWac36 oRI6ygHQ1eFvTcxXPl9QNhXvvX+uDyJfpfytyhqzCveRGV3Wh8tP4IE1Ob9MiLFoUH4LAX0GsA qIxUuZC4bcwz/Mbhz8oW/IAAAA= To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724762769; l=2792; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=vgn8uX1N5zG+nayIOSO9znCgxojVnlywzQCSUueGkXk=; b=16/ZCyzu/Dqhk0QPU0QlE98Ep+VbepBmFhIJBlVx7Dp3+Vo/rqbiYJ1ThOU1To2PmiztMokVs tZo9WGBlgRPAHvR4Hec2QjB+bPqAcuuPR2XFNDCL9j8zSVUyll+Tm6y X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ezc6HeO2vG4PYzlHHRhSuAAjTSvy9kYb X-Proofpoint-ORIG-GUID: ezc6HeO2vG4PYzlHHRhSuAAjTSvy9kYb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-27_06,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408270094 The CMN PLL clock controller in Qualcomm IPQ chipsets provides the clocks to the networking hardware blocks that are internal or external to the SoC. This driver configures the CMN PLL clock controller to enable the output clocks to such networking hardware blocks. These networking blocks include the internal PPE (Packet Process Engine), external connected Ethernet PHY, or external switch. The controller expects the input reference clock from the internal Wi-Fi block acting as the clock source. The output clocks supplied by the controller are fixed rate clocks. The CMN PLL hardware block does not include any other function other than enabling the clocks to the networking hardware blocks. The driver is being enabled to support IPQ9574 SoC initially, and will be extended for other SoCs. Signed-off-by: Luo Jie --- Changes in v3: - Update description of dt-binding to explain scope of 'CMN' in CMN PLL. - Collect Reviewed-by tags for dtbindings and defconfig patches. - Enable PLL_LOCKED check for the stability of output clocks. - Link to v2: https://lore.kernel.org/r/20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com Changes in v2: - Rename the dt-binding file with the compatible. - Remove property 'clock-output-names' from dt-bindings and define names in the driver. Add qcom,ipq-cmn-pll.h to export the output clock specifier. - Alphanumeric ordering of 'cmn_pll_ref_clk' node in DTS. - Fix allmodconfig error reported by test robot. - Replace usage of "common" to "CMN" to match the name with the hardware specification. - Clarify in commit message on scope of CMN PLL function. - Link to v1: https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com --- Luo Jie (4): dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC clk: qcom: Add CMN PLL clock controller driver for IPQ SoC arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 72 ++++++ arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +- arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ipq-cmn-pll.c | 241 +++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 ++ 8 files changed, 361 insertions(+), 2 deletions(-) --- base-commit: 222a3380f92b8791d4eeedf7cd750513ff428adf change-id: 20240808-qcom_ipq_cmnpll-7c1119b25037 Best regards,