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[93.84.1.20]) by smtp.googlemail.com with ESMTPSA id 38308e7fff4ca-2f8d289ee94sm7863791fa.120.2024.09.26.03.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 03:38:40 -0700 (PDT) From: Dzmitry Sankouski Subject: [PATCH v5 0/2] Add divisor computation feature for sdm845 gp clocks Date: Thu, 26 Sep 2024 13:38:14 +0300 Message-Id: <20240617-starqltechn_integration_upstream-v5-0-761795ea5084@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAJY59WYC/43O0Q6CIBQG4FdxXEdDULCueo/WHOJR2RQNkNWc7 x66tbqry//fzvefBTmwGhw6JwuyELTTo4khPyRIddK0gHUdM6KEZoSnAjsv7b33oDpTauOhtdL Hm3KenLcgB1ypghc5qWgDDEWmkg5wZaVRXYTM3PexnCw0+rHvXm8xd9r50T73NwLb2vdi8XsxM EwwsIZzTkkqpLq0g9T9UY0D2vCQfcBTyv4AswjSmkJT5yovhPgG13V9Ad5rAaM2AQAA To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dzmitry Sankouski X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727347119; l=2239; i=dsankouski@gmail.com; s=20240619; h=from:subject:message-id; bh=+qcwPAH5CWuhj09/E6HWAImsCw7nT/5uSGGKzcjVS5Q=; b=gKZKCAqwrb0LGnUPDlBsxmlEX2n5s0TnAxf+aVPZ7zOFtEruk54QeV3Z+VwedfLj+ZboKLyTK 46AfT6x+LZ6Am0bMvj1ox4Ek/xUn0lzOLUQyQOfiThn6TPQropQiChQ X-Developer-Key: i=dsankouski@gmail.com; a=ed25519; pk=YJcXFcN1EWrzBYuiE2yi5Mn6WLn6L1H71J+f7X8fMag= SDM845 has "General Purpose" clocks that can be muxed to SoC pins to clock various external devices. Those clocks may be used as e.g. PWM sources for external peripherals. GPCLK can in theory have arbitrary value depending on the use case, so the concept of frequency tables, used in rcg2 clock driver, is not efficient, because it allows only defined frequencies. Introduce clk_rcg2_gp_ops, which automatically calculate clock mnd values for arbitrary clock rate. The calculation done as follows: - upon determine rate request, we calculate m/n/pre_div as follows: - find parent(from our client's assigned-clock-parent) rate - find scaled rates by dividing rates on its greatest common divisor - assign requested scaled rate to m - factorize scaled parent rate, put multipliers to n till max value (determined by mnd_width) - validate calculated values with *_width: - if doesn't fit, delete divisor and multiplier by 2 until fit - return determined rate Limitations: - The driver doesn't select a parent clock (it may be selected by client in device tree with assigned-clocks, assigned-clock-parents properties) Signed-off-by: Dzmitry Sankouski --- Changes in v5: - Split patchset per subsystem - Link to v4: https://lore.kernel.org/r/20240913-starqltechn_integration_upstream-v4-0-2d2efd5c5877@gmail.com Changes in v4: - Replace gcc-845 freq_tbl frequencies patch with new approach, based on automatic m/n/pre_div value generation - Link to v3: https://lore.kernel.org/r/20240618-starqltechn_integration_upstream-v3-0-e3f6662017ac@gmail.com --- Dzmitry Sankouski (2): clk: qcom: clk-rcg2: document calc_rate function gcc-sdm845: Add general purpose clock ops drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 201 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---- drivers/clk/qcom/gcc-sdm845.c | 11 ++---- 3 files changed, 198 insertions(+), 15 deletions(-) --- base-commit: 92fc9636d1471b7f68bfee70c776f7f77e747b97 change-id: 20240617-starqltechn_integration_upstream-bc86850b2fe3 Best regards,