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Fri, 14 Jun 2024 01:35:36 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca282f1dbsm444776e87.110.2024.06.14.01.35.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 01:35:36 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH v2 0/2] phy: qcom: qmp-pcie: drop second clock-output-names entry Date: Fri, 14 Jun 2024 11:35:33 +0300 Message-Id: <20240614-fix-pcie-phy-compat-v2-0-990863ea53bf@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIANUAbGYC/32NQQ7CIBBFr9LM2jGA1FRX3sN0AXTaTqKFQENsG u4u9gAu38//7++QKDIluDc7RMqc2C8V1KkBN5tlIuShMiihtGiVxJE/GBwThnlD59/BrGjFOGi y+moHA3UZItXaYX32lWdOq4/bcZLlL/3vyxIFdsZo2dqbuoju8eLFRH/2cYK+lPIF25jAkLcAA AA= To: Vinod Koul , Kishon Vijay Abraham I , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1313; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=aXVVMd280kDEU99slp/goCJdHS5H7XE36h5Z2IJXkXg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmbADXrUm9cJ44C/Qoh4AWATZBW3PHxHeKo1RHh gPK0/xfq4WJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmwA1wAKCRCLPIo+Aiko 1QuOB/kBXJliWLone1Vftys+maL+YWswmOnQbrJaQc6CEa3Mie9hAeLIx8NBcEIIXS5NYMOuOOd UCghRsR0hPuJmF0uhQZ8fSVchGAjzz01YWZbj7PVsdM0EX20qN5EWZAPhrUY5n23FqZiVnujqL7 lwh+pD6jiErEGx4UZWJS6/4SHCK7h8Grzgi+h7Gsvl5TKrmwIXG6CxIcgTJeux46gUm/ak5tjza qUc3JlGHT4cAKtobXjt7QAqIVGDxSH7OQrnBYIN3WUnWP0wK/v8WbYwZVF4xuEqjXQ89NLYOhzb 6aM5Mwg1u1mmPX4hmyuh3856QQGpinpPcwVipkAywFo8+ZVF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A While testing the linux-next on SM8450-HDK I noticed that one of the PCIe hosts stays in the deferred state, because the corresponding PHY isn't probed. A quick debug pointed out that while the patches that added support for the PIPE AUX clock to the PHY driver have landed, corresponding DT changes were not picked up for 6.10. Restore the compatibility with the existing DT files by dropping the second entry in the clock-output-names array and always generating the corresponding name on the fly. Signed-off-by: Dmitry Baryshkov --- Changes in v2: - Fixed generated AUX clock name (Neil) - Link to v1: https://lore.kernel.org/r/20240521-fix-pcie-phy-compat-v1-0-8aa415b92308@linaro.org --- Dmitry Baryshkov (2): phy: qcom: qmp-pcie: restore compatibility with existing DTs dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +------ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------ 2 files changed, 4 insertions(+), 12 deletions(-) --- base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0 change-id: 20240521-fix-pcie-phy-compat-b0fd4eb46bda Best regards,