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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:22 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v2 0/7] Add SMEM-based speedbin matching Date: Wed, 05 Jun 2024 22:10:13 +0200 Message-Id: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIACXGYGYC/22NQQqDMBREryJ/3ZQkaJGueo8ixSSjfqiJJBJax Ls3Fbors3oD82ajhMhIdK02isicOPgC+lSRnXo/QrArTFrqWpaINSxsRZoxP9ICOMNetA6wTho MElSWS8TAr8N67wpPnNYQ38dJVt/252v++rISUlho015q3Sijbk/2fQznEEfq9n3/AOJYqwO3A AAA To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore, but instead rely on a set of combinations of "feature code" (FC) and "product code" (PC) identifiers to match the bins. This series adds support for that. I suppose a qcom/for-soc immutable branch would be in order if we want to land this in the upcoming cycle. FWIW I preferred the fuses myself.. Signed-off-by: Konrad Dybcio --- Changes in v3: - Wrap the argument usage in new preprocessor macros in braces (Bjorn) - Make the SOCINFO_FC_INT_MAX define inclusive, adjust .h and .c (Bjorn) - Pick up rbs - Rebase on next-20240605 - Drop the already-applied ("Avoid a nullptr dereference when speedbin setting fails") Changes in v2: - Separate moving existing and adding new defines - Fix kerneldoc copypasta - Remove some wrong comments and defines - Remove assumed "max" values for PCs and external FCs - Improve some commit messages - Return -EOPNOTSUPP instead of -EINVAL when calling p/fcode getters on socinfo older than v16 - Drop pcode getters and evaluation (doesn't matter for Adreno on non-proto SoCs) - Rework the speedbin logic to be hopefully saner - Link to v1: https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org --- Konrad Dybcio (7): soc: qcom: Move some socinfo defines to the header soc: qcom: smem: Add a feature code getter drm/msm/adreno: Implement SMEM-based speed bin drm/msm/adreno: Add speedbin data for SM8550 / A740 drm/msm/adreno: Define A530 speed bins explicitly drm/msm/adreno: Redo the speedbin assignment arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 +++++++- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 ------------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 54 ------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 84 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 ++-- drivers/soc/qcom/smem.c | 33 ++++++++++++ drivers/soc/qcom/socinfo.c | 8 --- include/linux/soc/qcom/smem.h | 1 + include/linux/soc/qcom/socinfo.h | 34 ++++++++++++ 10 files changed, 185 insertions(+), 107 deletions(-) --- base-commit: 234cb065ad82915ff8d06ce01e01c3e640b674d2 change-id: 20240404-topic-smem_speedbin-8deecd0bef0e Best regards,