| Message ID | 20240531090249.10293-1-quic_tdas@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support for SA8775P Multimedia clock controllers | expand |
On 31/05/2024 11:02, Taniya Das wrote: > Set FORCE_MEM_CORE_ON bit for gcc_ufs_phy_ice_core_clk. Why? > > Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") What bug are you fixing? Best regards, Krzysztof
On Fri, 31 May 2024 14:32:47 +0530, Taniya Das wrote: > Add device tree bindings for the display clock controller > on Qualcomm SA8775P platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sa8775p-dispcc.yaml | 88 +++++++++++++++++++ > .../dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++ > 2 files changed, 175 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-dispcc.h > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.example.dtb: /example-0/clock-controller@af00000: failed to match any schema with compatible: ['qcom,sa8755p-dispcc0'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240531090249.10293-12-quic_tdas@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 31.05.2024 11:02 AM, Taniya Das wrote: > The RCG's clk src has to be parked at XO while disabling as per the > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > Also gpu_cc_cb_clk is recommended to be kept always ON, hence use > clk_branch2_aon_ops to keep the clock always ON. > > Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- Should the same fixes apply to 8350? Konrad
On 31/05/2024 11:02, Taniya Das wrote: > Add device tree bindings for the video clock controller on Qualcomm > SA8775P platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 +++++++++++++++++++ > .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > new file mode 100644 > index 000000000000..3edb29d0e5eb > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Video Clock & Reset Controller on SA8775P > + > +maintainers: > + - Taniya Das <quic_tdas@quicinc.com> > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on SA8775P. > + > + See also:: include/dt-bindings/clock/qcom,sa8775p-videocc.h Just single ':' > + > +properties: > + compatible: > + enum: > + - qcom,sa8775p-videocc I am not sure if you are sure what you are doing... so to clarify: SA8775p is going significant bindings rework, so in general please post bindings matching new firmware (so SCMI consensus) or something which will be stable. Don't post something which tomorrow will need changes. Does this binding fits new style or is going to be considered stable? > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Video AHB clock from GCC > + - description: Board XO source > + - description: Board active XO source > + - description: Sleep Clock source > + > + power-domains: > + maxItems: 1 > + description: > + MMCX power domain. > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' Drop redundant properties and reference qcom,gcc.yaml. > +#endif Best regards, Krzysztof
On Fri, May 31, 2024 at 02:32:36PM GMT, Taniya Das wrote: > Update GCC, GPUCC clock controllers and add support for multimedia > clock controllers on Qualcomm SA8775P platform. > Most of the patches in this series does not depend on each other and some of them could have been merged already, if they weren't stacked in the middle of the series. Please lump patches together into series only when there is a dependency between them. The one exception here is the dts change at the end that has a dependency on the multiple binding updates. You can choose to either split this into multiple updates, or send it separately once the clock changes has been accepted. Thanks, Bjorn > Taniya Das (13): > clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks > clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags > clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for > gcc_ufs_phy_ice_core_clk > clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON > flags > clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable > clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's > dt-bindings: clock: qcom: Add SA8775P video clock controller > clk: qcom: Add support for Video clock controller on SA8775P > dt-bindings: clock: qcom: Add SA8775P camera controller > clk: qcom: Add support for Camera Clock Controller on SA8775P > dt-bindings: clock: qcom: Add SA8775P display controller > clk: qcom: Add support for Display Controllers on SA8775P > arm64: dts: qcom: Add support for multimedia clock controllers > > .../bindings/clock/qcom,sa8775p-camcc.yaml | 76 + > .../bindings/clock/qcom,sa8775p-dispcc.yaml | 88 + > .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 + > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 +- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 59 + > drivers/clk/qcom/Kconfig | 31 + > drivers/clk/qcom/Makefile | 3 + > drivers/clk/qcom/camcc-sa8775p.c | 1849 +++++++++++++++++ > drivers/clk/qcom/dispcc0-sa8775p.c | 1481 +++++++++++++ > drivers/clk/qcom/dispcc1-sa8775p.c | 1481 +++++++++++++ > drivers/clk/qcom/gcc-sa8775p.c | 154 +- > drivers/clk/qcom/gpucc-sa8775p.c | 41 +- > drivers/clk/qcom/videocc-sa8775p.c | 576 +++++ > .../dt-bindings/clock/qcom,sa8775p-camcc.h | 107 + > .../dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 + > .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 + > 16 files changed, 6027 insertions(+), 130 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml > create mode 100644 drivers/clk/qcom/camcc-sa8775p.c > create mode 100644 drivers/clk/qcom/dispcc0-sa8775p.c > create mode 100644 drivers/clk/qcom/dispcc1-sa8775p.c > create mode 100644 drivers/clk/qcom/videocc-sa8775p.c > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-camcc.h > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-dispcc.h > create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h > > -- > 2.17.1 >
On 5/31/2024 3:27 PM, Krzysztof Kozlowski wrote: > On 31/05/2024 11:02, Taniya Das wrote: >> Set FORCE_MEM_CORE_ON bit for gcc_ufs_phy_ice_core_clk. > > Why? > Yes, my bad I didn't update the commit text for this series. Force mem core bit for UFS ICE clock is required to retain the logic in memories of the subsystem across power states. Will update the commit text with these details in next series. >> >> Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") > > What bug are you fixing? > > > Best regards, > Krzysztof >
On 5/31/2024 6:53 PM, Konrad Dybcio wrote: > On 31.05.2024 11:02 AM, Taniya Das wrote: >> The RCG's clk src has to be parked at XO while disabling as per the >> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >> Also gpu_cc_cb_clk is recommended to be kept always ON, hence use >> clk_branch2_aon_ops to keep the clock always ON. >> >> Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- > > Should the same fixes apply to 8350? > Yes Konrad, it is applicable for 8350 as well. > Konrad
On 5/31/2024 7:29 PM, Krzysztof Kozlowski wrote: > On 31/05/2024 11:02, Taniya Das wrote: >> Add device tree bindings for the video clock controller on Qualcomm >> SA8775P platform. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 +++++++++++++++++++ >> .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++ >> 2 files changed, 122 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> new file mode 100644 >> index 000000000000..3edb29d0e5eb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> @@ -0,0 +1,75 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Video Clock & Reset Controller on SA8775P >> + >> +maintainers: >> + - Taniya Das <quic_tdas@quicinc.com> >> + >> +description: | >> + Qualcomm video clock control module provides the clocks, resets and power >> + domains on SA8775P. >> + >> + See also:: include/dt-bindings/clock/qcom,sa8775p-videocc.h > > Just single ':' > Will be fixed. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sa8775p-videocc > > I am not sure if you are sure what you are doing... so to clarify: > SA8775p is going significant bindings rework, so in general please post > bindings matching new firmware (so SCMI consensus) or something which > will be stable. > > Don't post something which tomorrow will need changes. > > Does this binding fits new style or is going to be considered stable? > Both these approaches should be supported for SA8775p. 1. SCMI to control the clock/NoC resources. 2. Clocks to be controlled via High Level OS(e.g. VideoCC driver). The expectation of the 1st approach is not to change/update any driver supported. Hope I am able to clarify. Please let me know if you have more queries on the same. >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Video AHB clock from GCC >> + - description: Board XO source >> + - description: Board active XO source >> + - description: Sleep Clock source >> + >> + power-domains: >> + maxItems: 1 >> + description: >> + MMCX power domain. >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - power-domains >> + - '#clock-cells' >> + - '#reset-cells' >> + - '#power-domain-cells' > > Drop redundant properties and reference qcom,gcc.yaml. > I will update in the next series. >> +#endif > > Best regards, > Krzysztof >
On 6/2/2024 9:52 AM, Bjorn Andersson wrote: > On Fri, May 31, 2024 at 02:32:36PM GMT, Taniya Das wrote: >> Update GCC, GPUCC clock controllers and add support for multimedia >> clock controllers on Qualcomm SA8775P platform. >> > > Most of the patches in this series does not depend on each other and > some of them could have been merged already, if they weren't stacked in > the middle of the series. > > Please lump patches together into series only when there is a dependency > between them. > > The one exception here is the dts change at the end that has a > dependency on the multiple binding updates. You can choose to either > split this into multiple updates, or send it separately once the clock > changes has been accepted. > Sure Bjorn, I will split the current series to two series. 1st to consolidate all the fixes and the New Drivers(Multimedia Clocks) in another series and will keep the DT in the next series. > Thanks, > Bjorn > >> Taniya Das (13): >> clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks >> clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags >> clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for >> gcc_ufs_phy_ice_core_clk >> clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON >> flags >> clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable >> clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's >> dt-bindings: clock: qcom: Add SA8775P video clock controller >> clk: qcom: Add support for Video clock controller on SA8775P >> dt-bindings: clock: qcom: Add SA8775P camera controller >> clk: qcom: Add support for Camera Clock Controller on SA8775P >> dt-bindings: clock: qcom: Add SA8775P display controller >> clk: qcom: Add support for Display Controllers on SA8775P >> arm64: dts: qcom: Add support for multimedia clock controllers >> >> .../bindings/clock/qcom,sa8775p-camcc.yaml | 76 + >> .../bindings/clock/qcom,sa8775p-dispcc.yaml | 88 + >> .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 + >> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 +- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 59 + >> drivers/clk/qcom/Kconfig | 31 + >> drivers/clk/qcom/Makefile | 3 + >> drivers/clk/qcom/camcc-sa8775p.c | 1849 +++++++++++++++++ >> drivers/clk/qcom/dispcc0-sa8775p.c | 1481 +++++++++++++ >> drivers/clk/qcom/dispcc1-sa8775p.c | 1481 +++++++++++++ >> drivers/clk/qcom/gcc-sa8775p.c | 154 +- >> drivers/clk/qcom/gpucc-sa8775p.c | 41 +- >> drivers/clk/qcom/videocc-sa8775p.c | 576 +++++ >> .../dt-bindings/clock/qcom,sa8775p-camcc.h | 107 + >> .../dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 + >> .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 + >> 16 files changed, 6027 insertions(+), 130 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml >> create mode 100644 drivers/clk/qcom/camcc-sa8775p.c >> create mode 100644 drivers/clk/qcom/dispcc0-sa8775p.c >> create mode 100644 drivers/clk/qcom/dispcc1-sa8775p.c >> create mode 100644 drivers/clk/qcom/videocc-sa8775p.c >> create mode 100644 include/dt-bindings/clock/qcom,sa8775p-camcc.h >> create mode 100644 include/dt-bindings/clock/qcom,sa8775p-dispcc.h >> create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h >> >> -- >> 2.17.1 >>
On Mon, Jun 10, 2024 at 02:41:10PM +0530, Taniya Das wrote: > > > On 5/31/2024 6:53 PM, Konrad Dybcio wrote: > > On 31.05.2024 11:02 AM, Taniya Das wrote: > > > The RCG's clk src has to be parked at XO while disabling as per the > > > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > > > Also gpu_cc_cb_clk is recommended to be kept always ON, hence use > > > clk_branch2_aon_ops to keep the clock always ON. > > > > > > Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") > > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > > > --- > > > > Should the same fixes apply to 8350? > > > > Yes Konrad, it is applicable for 8350 as well. Can we please get the corresponding patches (as a separate patchset)?
On 6/10/2024 11:44 PM, Dmitry Baryshkov wrote: > On Mon, Jun 10, 2024 at 02:41:10PM +0530, Taniya Das wrote: >> >> >> On 5/31/2024 6:53 PM, Konrad Dybcio wrote: >>> On 31.05.2024 11:02 AM, Taniya Das wrote: >>>> The RCG's clk src has to be parked at XO while disabling as per the >>>> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >>>> Also gpu_cc_cb_clk is recommended to be kept always ON, hence use >>>> clk_branch2_aon_ops to keep the clock always ON. >>>> >>>> Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") >>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>> --- >>> >>> Should the same fixes apply to 8350? >>> >> >> Yes Konrad, it is applicable for 8350 as well. > > Can we please get the corresponding patches (as a separate patchset)? > I will send the patch for 8350.
On Wed, Jun 12, 2024 at 04:00:47PM +0530, Taniya Das wrote: > > > On 6/10/2024 11:44 PM, Dmitry Baryshkov wrote: > > On Mon, Jun 10, 2024 at 02:41:10PM +0530, Taniya Das wrote: > > > > > > > > > On 5/31/2024 6:53 PM, Konrad Dybcio wrote: > > > > On 31.05.2024 11:02 AM, Taniya Das wrote: > > > > > The RCG's clk src has to be parked at XO while disabling as per the > > > > > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > > > > > Also gpu_cc_cb_clk is recommended to be kept always ON, hence use > > > > > clk_branch2_aon_ops to keep the clock always ON. > > > > > > > > > > Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") > > > > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > > > > > --- > > > > > > > > Should the same fixes apply to 8350? > > > > > > > > > > Yes Konrad, it is applicable for 8350 as well. > > > > Can we please get the corresponding patches (as a separate patchset)? > > > I will send the patch for 8350. Sounds great!
On 6/10/2024 11:44 PM, Dmitry Baryshkov wrote: > On Mon, Jun 10, 2024 at 02:41:10PM +0530, Taniya Das wrote: >> >> >> On 5/31/2024 6:53 PM, Konrad Dybcio wrote: >>> On 31.05.2024 11:02 AM, Taniya Das wrote: >>>> The RCG's clk src has to be parked at XO while disabling as per the >>>> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >>>> Also gpu_cc_cb_clk is recommended to be kept always ON, hence use >>>> clk_branch2_aon_ops to keep the clock always ON. >>>> >>>> Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") >>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>> --- >>> >>> Should the same fixes apply to 8350? >>> >> >> Yes Konrad, it is applicable for 8350 as well. > > Can we please get the corresponding patches (as a separate patchset)? > Please find the patch. https://lore.kernel.org/lkml/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com/T/#u
Update GCC, GPUCC clock controllers and add support for multimedia clock controllers on Qualcomm SA8775P platform. Taniya Das (13): clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's dt-bindings: clock: qcom: Add SA8775P video clock controller clk: qcom: Add support for Video clock controller on SA8775P dt-bindings: clock: qcom: Add SA8775P camera controller clk: qcom: Add support for Camera Clock Controller on SA8775P dt-bindings: clock: qcom: Add SA8775P display controller clk: qcom: Add support for Display Controllers on SA8775P arm64: dts: qcom: Add support for multimedia clock controllers .../bindings/clock/qcom,sa8775p-camcc.yaml | 76 + .../bindings/clock/qcom,sa8775p-dispcc.yaml | 88 + .../bindings/clock/qcom,sa8775p-videocc.yaml | 75 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 59 + drivers/clk/qcom/Kconfig | 31 + drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/camcc-sa8775p.c | 1849 +++++++++++++++++ drivers/clk/qcom/dispcc0-sa8775p.c | 1481 +++++++++++++ drivers/clk/qcom/dispcc1-sa8775p.c | 1481 +++++++++++++ drivers/clk/qcom/gcc-sa8775p.c | 154 +- drivers/clk/qcom/gpucc-sa8775p.c | 41 +- drivers/clk/qcom/videocc-sa8775p.c | 576 +++++ .../dt-bindings/clock/qcom,sa8775p-camcc.h | 107 + .../dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 + .../dt-bindings/clock/qcom,sa8775p-videocc.h | 47 + 16 files changed, 6027 insertions(+), 130 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml create mode 100644 drivers/clk/qcom/camcc-sa8775p.c create mode 100644 drivers/clk/qcom/dispcc0-sa8775p.c create mode 100644 drivers/clk/qcom/dispcc1-sa8775p.c create mode 100644 drivers/clk/qcom/videocc-sa8775p.c create mode 100644 include/dt-bindings/clock/qcom,sa8775p-camcc.h create mode 100644 include/dt-bindings/clock/qcom,sa8775p-dispcc.h create mode 100644 include/dt-bindings/clock/qcom,sa8775p-videocc.h -- 2.17.1