| Message ID | 20240527-msm-drm-dsc-dsi-video-upstream-4-v5-0-f797ffba4682@linaro.org |
|---|---|
| Headers | show |
| Series | Add DSC support to DSI video panel | expand |
On 27/05/2024 16:21, Jun Nie wrote: > This is follow up update to Jonathan's patch set. > > Changes vs V4: > - Polish width calculation with helper function > - Split cfg2 compression bit into another patch > > Changes vs V3: > - Rebase to latest msm-next-lumag branch. > - Drop the slice_per_pkt change as it does impact basic DSC feature. > - Remove change in generated dsi header > - update DSC compressed width calculation with bpp and bpc > - split wide bus impact on width into another patch > - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change > - Polish warning usage > - Add tags from reviewers > > Changes vs V2: > - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in > latest mainline code. > - Drop the bonded DSI patch as I do not have device to test it. > - Address comments from version 2. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > Changes in v5: > - Link to v4: https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c05b403df@linaro.org > > --- > Jonathan Marek (4): > drm/msm/dpu: fix video mode DSC for DSI > drm/msm/dsi: set video mode widebus enable bit when widebus is enabled > drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC > drm/msm/dsi: add a comment to explain pkt_per_line encoding > > Jun Nie (2): > drm/msm/dpu: adjust data width for widen bus case > drm/msm/dpu: enable compression bit in cfg2 for DSC > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 +++++++++++++ > drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +++++++++- > 5 files changed, 49 insertions(+), 2 deletions(-) > --- > base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 > change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 > > Best regards, Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK with https://lore.kernel.org/all/20230728012623.22991-1-quic_parellan@quicinc.com/ and enforce-video-mode in panel node. Thanks, Neil
On 5/27/2024 7:21 AM, Jun Nie wrote: > From: Jonathan Marek <jonathan@marek.ca> > > Add width change in DPU timing for DSC compression case to work with > DSI video mode. Hi Jun, LGTM Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Thanks, Jessica Zhang > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++++++++++++++++ > 3 files changed, 27 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 119f3ea50a7c..48cef6e79c70 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) > return (num_dsc > 0) && (num_dsc > intf_count); > } > > -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) > +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) > { > struct msm_drm_private *priv = drm_enc->dev->dev_private; > struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 002e89cc1705..2167c46c1a45 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > */ > unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); > > +/** > + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder > + * This helper function is used by physical encoder to get DSC config > + * used for this encoder. > + * @drm_enc: Pointer to encoder structure > + */ > +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); > + > /** > * dpu_encoder_get_drm_fmt - return DRM fourcc format > * @phys_enc: Pointer to physical encoder structure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ef69c2f408c3..925ec6ada0e1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -11,6 +11,7 @@ > #include "dpu_trace.h" > #include "disp/msm_disp_snapshot.h" > > +#include <drm/display/drm_dsc_helper.h> > #include <drm/drm_managed.h> > > #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ > @@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params( > timing->h_front_porch = timing->h_front_porch >> 1; > timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; > } > + > + /* > + * for DSI, if compression is enabled, then divide the horizonal active > + * timing parameters by compression ratio. bits of 3 components(R/G/B) > + * is compressed into bits of 1 pixel. > + */ > + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { > + struct drm_dsc_config *dsc = > + dpu_encoder_get_dsc_config(phys_enc->parent); > + /* > + * TODO: replace drm_dsc_get_bpp_int with logic to handle > + * fractional part if there is fraction > + */ > + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / > + (dsc->bits_per_component * 3); > + timing->xres = timing->width; > + } > } > > static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) > > -- > 2.34.1 >
On 5/27/2024 7:21 AM, Jun Nie wrote: > From: Jonathan Marek <jonathan@marek.ca> > > Video mode DSC won't work if this field is not set correctly. Set it to fix > video mode DSC (for slice_per_pkt==1 cases at least). > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Jun Nie <jun.nie@linaro.org> Hi Jun, Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Thanks, Jessica Zhang > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index 47f5858334f6..7252d36687e6 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -857,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > u32 slice_per_intf, total_bytes_per_intf; > u32 pkt_per_line; > u32 eol_byte_num; > + u32 bytes_per_pkt; > > /* first calculate dsc parameters and then program > * compress mode registers > @@ -864,6 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); > > total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; > + bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ > > eol_byte_num = total_bytes_per_intf % 3; > > @@ -901,6 +903,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); > dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); > } else { > + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); > dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); > } > } > > -- > 2.34.1 >
On 5/27/2024 7:21 AM, Jun Nie wrote: > Enable compression bit in cfg2 register for DSC in the DSI case > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index f97221423249..34bfcfba3df2 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > if (p->wide_bus_en && !dp_intf) > data_width = p->width >> 1; > > + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ > + if (p->compression_en && !dp_intf) > + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; Hi Jun, The DSC/DCE enablement registers were only moved to INTF in DPU 7.x and later. We should probably add some MDSS version check similar to what command mode INTF does here [1] Thanks, Jessica Zhang > + > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > > -- > 2.34.1 >
This is follow up update to Jonathan's patch set. Changes vs V4: - Polish width calculation with helper function - Split cfg2 compression bit into another patch Changes vs V3: - Rebase to latest msm-next-lumag branch. - Drop the slice_per_pkt change as it does impact basic DSC feature. - Remove change in generated dsi header - update DSC compressed width calculation with bpp and bpc - split wide bus impact on width into another patch - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change - Polish warning usage - Add tags from reviewers Changes vs V2: - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- Changes in v5: - Link to v4: https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c05b403df@linaro.org --- Jonathan Marek (4): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC drm/msm/dsi: add a comment to explain pkt_per_line encoding Jun Nie (2): drm/msm/dpu: adjust data width for widen bus case drm/msm/dpu: enable compression bit in cfg2 for DSC drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 +++++++++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +++++++++- 5 files changed, 49 insertions(+), 2 deletions(-) --- base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 Best regards,