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Thu, 02 May 2024 01:00:41 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id t15-20020a05600c198f00b0041c02589a7csm4806597wmq.40.2024.05.02.01.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 May 2024 01:00:40 -0700 (PDT) From: Neil Armstrong Subject: [PATCH v5 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Date: Thu, 02 May 2024 10:00:35 +0200 Message-Id: <20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-0-10c650cfeade@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIACNIM2YC/53QTW7CMBCG4asgrzuV/x2z6j2qLszYEKsQW3YSB aHcvYZNQaxg+c3ieaW5kBpKDJVsNxdSwhxrTEMb6mNDsHfDIUD0bRNOuaSCWRhTjgj11C2KwpT rWII7QcYYgEHuz+CmBfD4C3InFNPWUOM9aVwuYR+XW+r7p+0+1jGV8608s+v1jcjMgILl2hsnE X1Hv45xcCV9pnIg18rM72TOX5B5k0VA6qzWXvH9kyz+ZfmSLJpsrJVGOW4Qw5Ms35Vlkzvd7Zh yrH1EPcjruv4BWDZvWu8BAAA= To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. The PHY driver needs a light refactoring to support a second clock, and finally the DT is changed to connect the PHY second clock to the corresponding GCC input then drop the dummy fixed rate clock. To: Bjorn Andersson To: Konrad Dybcio To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Neil Armstrong Changes in v5: - Reworked commit message to include more reasoning and details about the changes - Link to v4: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org Changes in v4: - Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next - Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org Changes in v3: - Rebased on linux-next, applies now cleanly - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org Changes in v2: - Collected review tags - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0 when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get() - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org --- Neil Armstrong (3): arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 ------------------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 8 files changed, 12 insertions(+), 57 deletions(-) --- base-commit: 1d0a6cdb7d77a14da03246bb6f10a489ad49af41 change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd Best regards,