| Message ID | 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock | expand |
On Mon, Apr 22, 2024 at 06:16:18PM GMT, Neil Armstrong wrote: > Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy > provided QMP_PCIE_PHY_AUX_CLK. > This looks applicable to the other two patches, but I don't see the pcie-1-phy-aux-clk being removed in this patch. Furthermore, the cover letter does not make it into the git history, which results in rather lacking documentation on the reasoning for the change. Can you please update the three commit messages? Regards, Bjorn > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 616461fcbab9..71797f337d19 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&sleep_clk>, > <&pcie0_phy>, > - <&pcie1_phy>, > - <0>, > + <&pcie1_phy QMP_PCIE_PIPE_CLK>, > + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, > <&ufs_mem_phy 0>, > <&ufs_mem_phy 1>, > <&ufs_mem_phy 2>, > @@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 { > "rchng", > "pipe"; > > - clock-output-names = "pcie_1_pipe_clk"; > - #clock-cells = <0>; > + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; > + #clock-cells = <1>; > > #phy-cells = <0>; > > > -- > 2.34.1 >
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. The PHY driver needs a light refactoring to support a second clock, and finally the DT is changed to connect the PHY second clock to the corresponding GCC input then drop the dummy fixed rate clock. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v4: - Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next - Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org Changes in v3: - Rebased on linux-next, applies now cleanly - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org Changes in v2: - Collected review tags - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0 when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get() - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org --- Neil Armstrong (3): arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 ------------------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 8 files changed, 12 insertions(+), 57 deletions(-) --- base-commit: f529a6d274b3b8c75899e949649d231298f30a32 change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd Best regards,