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Mon, 22 Jan 2024 05:57:09 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 21 Jan 2024 21:57:03 -0800 From: Kathiravan Thirumoorthy Subject: [PATCH v4 0/8] Add NSS clock controller support for Qualcomm IPQ5332 Date: Mon, 22 Jan 2024 11:26:56 +0530 Message-ID: <20240122-ipq5332-nsscc-v4-0-19fa30019770@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAKgDrmUC/3XMywrCMBCF4VcpWRuZTC5YV76HuIhjamdhL4kGp fTdTQsuFFyeA98/iRQihyT21SRiyJy478owm0pQ67trkHwpWyCgVqBB8jBarVF2KRFJHzzVQVk Nxopihhgafq6946nsltO9j681n3F5/5WykiCdcuiRnG3AH8YHE3e0pf4mllY2H29AIf56U7yul QIX6p0/228/z/MbaOfc8ewAAAA= To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Richard Cochran , "Catalin Marinas" , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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Some of the nssnoc clocks present in GCC driver is enabled by default and its RCG is configured by bootloaders, so enable those clocks in driver probe. The NSS clock controller driver depends on the below patchset which adds support for multiple configurations for same frequency. https://lore.kernel.org/linux-arm-msm/20231220221724.3822-1-ansuelsmth@gmail.com/ Signed-off-by: Kathiravan Thirumoorthy --- Changes in v4: - Rebased on next-20240122 - Fixed the missing space on the nsscc node - Link to v3: https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ Changes in v3: - Collected the tags - Dropped the dt-binding patch 3/9 - Cleaned up the header file inclusion and updated the module description in the driver - Used the decimal number instead of hex in the NSSCC node - Link to v2: https://lore.kernel.org/r/20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com Changes in v2: - Change logs are in respective patches - Link to v1: https://lore.kernel.org/r/20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com --- Kathiravan Thirumoorthy (8): clk: qcom: ipq5332: add const qualifier to the clk_init_data structure clk: qcom: ipq5332: enable few nssnoc clocks in driver probe dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock clk: qcom: ipq5332: add gpll0_out_aux clock dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332 arm64: dts: qcom: ipq5332: add support for the NSSCC arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332 .../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 ++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5332.c | 122 +-- drivers/clk/qcom/nsscc-ipq5332.c | 1031 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++ 9 files changed, 1260 insertions(+), 77 deletions(-) --- base-commit: 319fbd8fc6d339e0a1c7b067eed870c518a13a02 change-id: 20231030-ipq5332-nsscc-aeac9e153045 Best regards,