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[0/2] PCI: dwc: Fix the BAR size programming

Message ID 20231017-pcie-qcom-bar-v1-0-3e26de07bec0@linaro.org
Headers show
Series PCI: dwc: Fix the BAR size programming | expand

Message

Manivannan Sadhasivam Oct. 17, 2023, 6:17 a.m. UTC 
Hello,

This series fixes the issue seen on Qcom EP platforms implementing the DWC
core while setting the BAR size. Currently, whatever the BAR size getting
programmed through pci_epc_set_bar() is not reflected on the host side
during enumeration.

Debugging that issue revealed that the DWC Spec mandates asserting the DBI
CS2 register in addition to DBI CS while programming some read only and
shadow registers. On the Qcom EP platforms, the BAR mask register used to
program the BAR size is marked as read only (RO). So the driver needs to
assert DBI CS2 before programming and deassert it once done.

Hence, this series adds two new macros for asserting/deasserting the DBI
CS2 while programming BAR size and also introduces a new host callback,
dbi_cs2_access() that the vendor drivers can implement.

For platforms not requiring the DBI CS2 access, this is a no-op.

This series has been tested on Qcom SM8450 based development platform.

---
Manivannan Sadhasivam (2):
      PCI: dwc: Add new accessors to enable/disable DBI CS2 while setting the BAR size
      PCI: qcom-ep: Implement dbi_cs2_access() function callback for DBI CS2 access

 drivers/pci/controller/dwc/pcie-designware-ep.c |  6 ++++++
 drivers/pci/controller/dwc/pcie-designware.h    | 13 +++++++++++++
 drivers/pci/controller/dwc/pcie-qcom-ep.c       | 14 ++++++++++++++
 3 files changed, 33 insertions(+)
---
base-commit: a286439bbc71e8c9bb1660b7d4775efcab6011fa
change-id: 20231017-pcie-qcom-bar-c4863c33c0e4

Best regards,