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[v4,0/2] irqchip/qcom-pdc: support v3.2 HW

Message ID 20230905-topic-sm8x50-upstream-pdc-ver-v4-0-fc633c7df84b@linaro.org
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Series irqchip/qcom-pdc: support v3.2 HW | expand

Message

Neil Armstrong Sept. 5, 2023, 1:19 p.m. UTC
Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the
IRQ_i_CFG register and requires a change of the driver to avoid
writing into an undefined register address.

Get the HW version from registers and set the IRQ_ENABLE bit to the
correct register depending on the HW version.

Since SM8150 DT uses a too smal PDC reg size, it's required to:
- fix SM8150 DT
- extend the PDC reg from the driver if used with old unfixed DT

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v4:
- Continue Dmitry's serie at https://lore.kernel.org/all/20230829092119.1017194-1-dmitry.baryshkov@linaro.org/
- Dmitry's changes:
   - Fix PDC resource size if it is too short instead of setting version to dummy 0 value (Marc).
   - Squashed the fix into the original patch.
- Changes requested by Marc on Dmitry's serie:
   - explicit PDC_VERSION is a reg offset
   - remove the enum
   - move the enable_intr to a shared function
   - add a warning when reg size doesn't match max size
- Link to v3: https://lore.kernel.org/r/20230823-topic-sm8x50-upstream-pdc-ver-v3-1-aa7d9ab862e4@linaro.org

Changes in v3:
- Simplify qcom_pdc_gic_set_type()
- Used __assign_bit in pdc_setup_pin_mapping()
- remove BIT() from IRQ_i_CFG_IRQ_ENABLE to be used with __assign_bit()
- Add Reviewed-by tag
- Link to v2: https://lore.kernel.org/r/20230822-topic-sm8x50-upstream-pdc-ver-v2-1-3035b8d388f7@linaro.org

Changes in v2:
- Changed IRQ_ENABLE handling based on Maulik's comments
- Link to v1: https://lore.kernel.org/r/20230821-topic-sm8x50-upstream-pdc-ver-v1-1-6d7f4dd95719@linaro.org

---
Dmitry Baryshkov (1):
      arm64: dts: qcom: sm8150: extend the size of the PDC resource

Neil Armstrong (1):
      irqchip/qcom-pdc: Add support for v3.2 HW

 arch/arm64/boot/dts/qcom/sm8150.dtsi |  2 +-
 drivers/irqchip/qcom-pdc.c           | 69 ++++++++++++++++++++++++++----------
 2 files changed, 52 insertions(+), 19 deletions(-)
---
base-commit: 47d9bb711707d15b19fad18c8e2b4b027a264a3a
change-id: 20230821-topic-sm8x50-upstream-pdc-ver-114ceb45e1ee

Best regards,

Comments

Konrad Dybcio Sept. 6, 2023, 4:55 p.m. UTC | #1
On 5.09.2023 15:19, Neil Armstrong wrote:
> Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the
> IRQ_i_CFG register and requires a change of the driver to avoid
> writing into an undefined register address.
> 
> Get the HW version from registers and set the IRQ_ENABLE bit to the
> correct register depending on the HW version.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
[...]

> +	if (pdc_version < PDC_VERSION_3_2) {
> +		u32 index, mask;
> +
> +		index = pin_out / 32;
> +		mask = pin_out % 32;
I get that you're moving around existing code, but would that
not be equal to FIELD_GET() with GENMASK(31, 5) and GENMASK(4, 0)?
Perhaps it'd be clearer to read. But don't worry about it in this
series.

Otherwise:

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Neil Armstrong Sept. 7, 2023, 7:57 a.m. UTC | #2
Hi,

On 06/09/2023 18:55, Konrad Dybcio wrote:
> On 5.09.2023 15:19, Neil Armstrong wrote:
>> Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the
>> IRQ_i_CFG register and requires a change of the driver to avoid
>> writing into an undefined register address.
>>
>> Get the HW version from registers and set the IRQ_ENABLE bit to the
>> correct register depending on the HW version.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> [...]
> 
>> +	if (pdc_version < PDC_VERSION_3_2) {
>> +		u32 index, mask;
>> +
>> +		index = pin_out / 32;
>> +		mask = pin_out % 32;
> I get that you're moving around existing code, but would that
> not be equal to FIELD_GET() with GENMASK(31, 5) and GENMASK(4, 0)?
> Perhaps it'd be clearer to read. But don't worry about it in this
> series.

Yes it would, I took the best implementation of the two :-p

I will probably send a cleanup serie afterwards because there's some
cleanup to do all over the code.

Neil

> 
> Otherwise:
> 
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Konrad