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[v2,00/16] phy: qcom-qmp-usb: convert to newer style of bindings

Message ID 20230821002535.585660-1-dmitry.baryshkov@linaro.org
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Series phy: qcom-qmp-usb: convert to newer style of bindings | expand

Message

Dmitry Baryshkov Aug. 21, 2023, 12:25 a.m. UTC
Reviewing several patchsets for newer platforms made it clear that
having two styles of QMP PHY bindings causes confusion. Despite binding
documents having notes telling that old bindings should be used for
older platforms, it is too easy to attempt adding new platform with
older QMP PHY binding. Thus let's have just a single documented style of
bindings.

Proposed merge strategy: immutable branch with binding and PHY patches,
which can also be merged into Bjorn's dts-for-6.7

Changes since v1:
 - Split large patchset into smaller parts
 - Rebased on phy/next
 - Reworked bindings to follow the common standard rather than blindly
   moving the PHY contents.

Dmitry Baryshkov (16):
  dt-bindings: phy: migrate QMP USB PHY bindings to
    qcom,sc8280xp-qmp-usb3-uni-phy.yaml
  phy: qcom-qmp-usb: simplify clock handling
  phy: qcom-qmp-usb: rework reset handling
  phy: qcom-qmp-usb: make QPHY_PCS_MISC_CLAMP_ENABLE access conditional
  phy: qcom-qmp: move PCS MISC V4 registers to separate header
  phy: qcom-qmp-usb: populate offsets configuration
  arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: ipq8074: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: msm8996: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: msm8998: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: sdm845: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: sm8150: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: sm8250: switch USB QMP PHY to new style of bindings
  arm64: dts: qcom: sm8350: switch USB QMP PHY to new style of bindings
  ARM: dts: qcom-sdx55: switch USB QMP PHY to new style of bindings
  ARM: dts: qcom-sdx65: switch USB QMP PHY to new style of bindings

 .../phy/qcom,msm8996-qmp-usb3-phy.yaml        | 287 ------------------
 .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml   |  53 +++-
 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi        |  41 ++-
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi        |  35 +--
 arch/arm64/boot/dts/qcom/ipq6018.dtsi         |  35 +--
 arch/arm64/boot/dts/qcom/ipq8074.dtsi         |  76 ++---
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |  40 ++-
 arch/arm64/boot/dts/qcom/msm8998.dtsi         |  39 +--
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |  39 ++-
 arch/arm64/boot/dts/qcom/sm8150.dtsi          |  39 +--
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |  38 +--
 arch/arm64/boot/dts/qcom/sm8350.dtsi          |  39 +--
 .../phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h   |  17 ++
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c       | 225 +++++++-------
 drivers/phy/qualcomm/phy-qcom-qmp.h           |   8 -
 15 files changed, 352 insertions(+), 659 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
 create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h

Comments

Dmitry Baryshkov Aug. 23, 2023, 6:20 p.m. UTC | #1
On Mon, 21 Aug 2023 at 03:25, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> Change the USB QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++----------------
>  1 file changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 30d8730fa4de..46a6ef0e454b 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -979,12 +979,12 @@ pcie_phy: phy@1c06000 {
>                         status = "disabled";
>
>                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> -                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>                                  <&gcc GCC_PCIE_CLKREF_CLK>,
> +                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
>                         clock-names = "aux",
> -                                     "cfg_ahb",
>                                       "ref",
> +                                     "cfg_ahb",
>                                       "pipe";

This chunk changes the PCIe PHY and as such doesn't belong to this patch.

>
>                         clock-output-names = "pcie_0_pipe_clk_src";
> @@ -2138,7 +2138,7 @@ usb3_dwc3: usb@a800000 {
>                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
>                                 snps,dis_u2_susphy_quirk;
>                                 snps,dis_enblslpm_quirk;
> -                               phys = <&qusb2phy>, <&usb1_ssphy>;
> +                               phys = <&qusb2phy>, <&usb3phy>;
>                                 phy-names = "usb2-phy", "usb3-phy";
>                                 snps,has-lpm-erratum;
>                                 snps,hird-threshold = /bits/ 8 <0x10>;
> @@ -2147,33 +2147,26 @@ usb3_dwc3: usb@a800000 {
>
>                 usb3phy: phy@c010000 {
>                         compatible = "qcom,msm8998-qmp-usb3-phy";
> -                       reg = <0x0c010000 0x18c>;
> -                       status = "disabled";
> -                       #address-cells = <1>;
> -                       #size-cells = <1>;
> -                       ranges;
> +                       reg = <0x0c010000 0x1000>;
>
>                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
> +                                <&gcc GCC_USB3_CLKREF_CLK>,
>                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> -                                <&gcc GCC_USB3_CLKREF_CLK>;
> -                       clock-names = "aux", "cfg_ahb", "ref";
> +                                <&gcc GCC_USB3_PHY_PIPE_CLK>;
> +                       clock-names = "aux",
> +                                     "ref",
> +                                     "cfg_ahb",
> +                                     "pipe";
> +                       clock-output-names = "usb3_phy_pipe_clk_src";
> +                       #clock-cells = <0>;
> +                       #phy-cells = <0>;
>
>                         resets = <&gcc GCC_USB3_PHY_BCR>,
>                                  <&gcc GCC_USB3PHY_PHY_BCR>;
> -                       reset-names = "phy", "common";
> +                       reset-names = "phy",
> +                                     "phy_phy";
>
> -                       usb1_ssphy: phy@c010200 {
> -                               reg = <0xc010200 0x128>,
> -                                     <0xc010400 0x200>,
> -                                     <0xc010c00 0x20c>,
> -                                     <0xc010600 0x128>,
> -                                     <0xc010800 0x200>;
> -                               #phy-cells = <0>;
> -                               #clock-cells = <0>;
> -                               clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
> -                               clock-names = "pipe0";
> -                               clock-output-names = "usb3_phy_pipe_clk_src";
> -                       };
> +                       status = "disabled";
>                 };
>
>                 qusb2phy: phy@c012000 {
> --
> 2.39.2
>