From patchwork Thu Aug 10 11:54:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 712773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C6CC41513 for ; Thu, 10 Aug 2023 11:54:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232608AbjHJLyr (ORCPT ); Thu, 10 Aug 2023 07:54:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229848AbjHJLyq (ORCPT ); Thu, 10 Aug 2023 07:54:46 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2941136; Thu, 10 Aug 2023 04:54:45 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AALjkF021976; Thu, 10 Aug 2023 11:54:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=RnPMVJ0E3kytxu+Z1p+pHlrHkeIXYvpU/cENA2V4ecs=; b=cCxdTu9JxbbXJNlRGTYmiMl45mz3yem+NBt1f1YqO7fUwAQDln1qDMQSPh/49dPFArAv 7llJwT2m8lKYxdPljHkcUTMZUG5O0bIEVZczVxs+cg8Jz7uDhFhR8jmo8nZm5UMGNJ0l TrKT0IeDJkO0h8QKz2R4Fb6IhXRrSQFbYP/ShG7CqrfZ2tozWqXIPkgxOt8e1Rg+8/Fy jLRxm42jutNoW6Gi3205vBGi8Q+HmJMiAvMC2SqEFt6gQqnRVr3R7dArfbhVZ909zKJh Q/afBW49IzFlTKF6b9NO5nHqdomLfHzseryP7p7jppjlf6cyjfMwJkBTSMNmgr7CScNd 3g== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3scr39gxv5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Aug 2023 11:54:35 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37ABsYlc024761 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Aug 2023 11:54:34 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 10 Aug 2023 04:54:30 -0700 From: Luo Jie To: , , , , , , , , , , CC: , , , , , Luo Jie Subject: [PATCH v3 0/3] add clock controller of qca8386/qca8084 Date: Thu, 10 Aug 2023 19:54:16 +0800 Message-ID: <20230810115419.25539-1-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7HeM7SEYPDYkp1_j0BltRtqUPohzB1ZF X-Proofpoint-ORIG-GUID: 7HeM7SEYPDYkp1_j0BltRtqUPohzB1ZF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_10,2023-08-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308100100 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode named by qca8386, or working as PHY mode named by qca8084, clock hardware reigster is accessed by MDIO bus. This patch series add the clock controller of qca8363/qca8084, and add the clock ops clk_branch2_mdio_ops to avoid spin lock used during the clock operation of qca8k clock controller where the sleep happens when accessing clock control register by MDIO bus. Changes in v2: * remove clock flag CLK_ENABLE_MUTEX_LOCK. * add clock ops clk_branch2_qca8k_ops. * improve yaml file for fixing dtschema warnings. * enable clock controller driver in defconfig. Changes in v3: * rename clk_branch2_qca8k_ops to clk_branch2_mdio_ops. * fix review comments on yaml file. * use dev_err_probe on driver probe error. * only use the compatible "qcom,qca8084-nsscc". * remove enable clock controller driver patch. Luo Jie (3): clk: qcom: branch: Add clk_branch2_mdio_ops dt-bindings: clock: add qca8386/qca8084 clock and reset definitions clk: qcom: add clock controller driver for qca8386/qca8084 .../bindings/clock/qcom,qca8k-nsscc.yaml | 79 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-branch.c | 8 + drivers/clk/qcom/clk-branch.h | 2 + drivers/clk/qcom/nsscc-qca8k.c | 2180 +++++++++++++++++ include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 + include/dt-bindings/reset/qcom,qca8k-nsscc.h | 75 + 8 files changed, 2454 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-qca8k.c create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h base-commit: 29afcd69672a4e3d8604d17206d42004540d6d5c