| Message ID | 20230719041450.737929-1-quic_imrashai@quicinc.com |
|---|---|
| Headers | show |
| Series | Update GCC clocks for QDU1000 and QRU1000 SoCs | expand |
On Wed, Jul 19, 2023 at 09:44:44AM +0530, Imran Shaik wrote: > Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs. > Please read [1], and as it says "Describe your problem.". This goes for the most of the series. There are changes in this series which could be applicable to existing or future platforms. Your description of the problems you're solving will help others solve the same problem, not make the same mistake, and anyone fixing adjacent issues in the future can rely on your documentation of why things looks the way they look. [1] https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#describe-your-changes > Co-developed-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Please don't use co-developed-by excessively. This patch is beyond trivial, did you really both author it? Regards, Bjorn > Acked-by: Rob Herring <robh@kernel.org> > --- > Changes since v3: > - None > Changes since v2: > - None > Changes since v1: > - Removed the v2 variant compatible string changes > - Updated the maintainers list > > Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- > include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml > index 767a9d03aa32..d712b1a87e25 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 > > maintainers: > - - Melody Olvera <quic_molvera@quicinc.com> > + - Taniya Das <quic_tdas@quicinc.com> > + - Imran Shaik <quic_imrashai@quicinc.com> > > description: | > Qualcomm global clock control module which supports the clocks, resets and > diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h > index ddbc6b825e80..2fd36cbfddbb 100644 > --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h > +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > /* > - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H > @@ -138,6 +138,8 @@ > #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 > #define GCC_PCIE_0_PIPE_CLK_SRC 129 > #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 > +#define GCC_GPLL1_OUT_EVEN 131 > +#define GCC_DDRSS_ECPRI_GSI_CLK 132 > > /* GCC resets */ > #define GCC_ECPRI_CC_BCR 0 > -- > 2.25.1 >
On 7/19/2023 9:05 PM, Bjorn Andersson wrote: > On Wed, Jul 19, 2023 at 09:44:44AM +0530, Imran Shaik wrote: >> Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs. >> > > Please read [1], and as it says "Describe your problem.". This goes for > the most of the series. > > There are changes in this series which could be applicable to existing > or future platforms. Your description of the problems you're solving > will help others solve the same problem, not make the same mistake, and > anyone fixing adjacent issues in the future can rely on your > documentation of why things looks the way they look. > > [1] https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#describe-your-changes > Sure, will update the next series with the detailed commit text. >> Co-developed-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > > Please don't use co-developed-by excessively. This patch is beyond > trivial, did you really both author it? > > Regards, > Bjorn > Sure, will take care of this from now and will remove the co-developed-by for trivial changes in next series. Thanks, Imran >> Acked-by: Rob Herring <robh@kernel.org> >> --- >> Changes since v3: >> - None >> Changes since v2: >> - None >> Changes since v1: >> - Removed the v2 variant compatible string changes >> - Updated the maintainers list >> >> Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- >> include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- >> 2 files changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml >> index 767a9d03aa32..d712b1a87e25 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml >> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# >> title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 >> >> maintainers: >> - - Melody Olvera <quic_molvera@quicinc.com> >> + - Taniya Das <quic_tdas@quicinc.com> >> + - Imran Shaik <quic_imrashai@quicinc.com> >> >> description: | >> Qualcomm global clock control module which supports the clocks, resets and >> diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h >> index ddbc6b825e80..2fd36cbfddbb 100644 >> --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h >> +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h >> @@ -1,6 +1,6 @@ >> /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ >> /* >> - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H >> @@ -138,6 +138,8 @@ >> #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 >> #define GCC_PCIE_0_PIPE_CLK_SRC 129 >> #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 >> +#define GCC_GPLL1_OUT_EVEN 131 >> +#define GCC_DDRSS_ECPRI_GSI_CLK 132 >> >> /* GCC resets */ >> #define GCC_ECPRI_CC_BCR 0 >> -- >> 2.25.1 >>