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[0/6] Add NSS clock controller support for IPQ9574

Message ID 20230711093529.18355-1-quic_devipriy@quicinc.com
Headers show
Series Add NSS clock controller support for IPQ9574 | expand

Message

Devi Priya July 11, 2023, 9:35 a.m. UTC 
Add bindings, driver and devicetree node for networking sub system clock 
controller on IPQ9574. Also add support for NSS Huayra type alpha PLL and
mark few nssnoc clocks as critical which are required to be turned on for 
accessing nss port clocks.

The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/

Devi Priya (6):
  clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
  clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
  dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
  clk: qcom: Add NSS clock Controller driver for IPQ9574
  arm64: dts: qcom: ipq9574: Add support for nsscc node
  arm64: defconfig: Build NSS Clock Controller driver for IPQ9574

 .../bindings/clock/qcom,ipq9574-nsscc.yaml    |   76 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         |   44 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/qcom/Kconfig                      |    6 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-alpha-pll.c              |   12 +
 drivers/clk/qcom/clk-alpha-pll.h              |    1 +
 drivers/clk/qcom/gcc-ipq9574.c                |    6 +-
 drivers/clk/qcom/nsscc-ipq9574.c              | 3080 +++++++++++++++++
 .../dt-bindings/clock/qcom,ipq9574-nsscc.h    |  152 +
 .../dt-bindings/reset/qcom,ipq9574-nsscc.h    |  134 +
 11 files changed, 3510 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
 create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
 create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
 create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h


base-commit: fe57d0d86f03a8b2afe2869a95477d0ed1824c96

Comments

Simon Horman July 13, 2023, 5:37 a.m. UTC | #1 
On Tue, Jul 11, 2023 at 03:05:27PM +0530, Devi Priya wrote:
> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
> devices.
> 
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>

...

> +static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
> +	[NSS_CC_CE_BCR] = { 0x28400, 0 },
> +	[NSS_CC_CLC_BCR] = { 0x28600, 0 },
> +	[NSS_CC_EIP197_BCR] = { 0x16004, 0 },
> +	[NSS_CC_HAQ_BCR] = { 0x28300, 0 },
> +	[NSS_CC_IMEM_BCR] = { 0xe004, 0 },
> +	[NSS_CC_MAC_BCR] = { 0x28100, 0 },
> +	[NSS_CC_PPE_BCR] = { 0x28200, 0 },
> +	[NSS_CC_UBI_BCR] = { 0x28700, 0 },
> +	[NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
> +	[UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
> +	[UBI3_CORE_CLAMP_ENABLE] = { 0x28A04, 8 },
> +	[UBI2_CLKRST_CLAMP_ENABLE] = { 0x28A04, 7 },
> +	[UBI2_CORE_CLAMP_ENABLE] = { 0x28A04, 6 },
> +	[UBI1_CLKRST_CLAMP_ENABLE] = { 0x28A04, 5 },
> +	[UBI1_CORE_CLAMP_ENABLE] = { 0x28A04, 4 },
> +	[UBI0_CLKRST_CLAMP_ENABLE] = { 0x28A04, 3 },
> +	[UBI0_CORE_CLAMP_ENABLE] = { 0x28A04, 2 },
> +	[NSSNOC_NSS_CSR_ARES] = { 0x28A04, 1 },
> +	[NSS_CSR_ARES]  { 0x28A04, 0 },

Hi Devi,

There appears to be an '=' missing in the line above.

...
Devi Priya July 17, 2023, 6:36 a.m. UTC | #2 
On 7/13/2023 11:07 AM, Simon Horman wrote:
> On Tue, Jul 11, 2023 at 03:05:27PM +0530, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> 
> ...
> 
>> +static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
>> +	[NSS_CC_CE_BCR] = { 0x28400, 0 },
>> +	[NSS_CC_CLC_BCR] = { 0x28600, 0 },
>> +	[NSS_CC_EIP197_BCR] = { 0x16004, 0 },
>> +	[NSS_CC_HAQ_BCR] = { 0x28300, 0 },
>> +	[NSS_CC_IMEM_BCR] = { 0xe004, 0 },
>> +	[NSS_CC_MAC_BCR] = { 0x28100, 0 },
>> +	[NSS_CC_PPE_BCR] = { 0x28200, 0 },
>> +	[NSS_CC_UBI_BCR] = { 0x28700, 0 },
>> +	[NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
>> +	[UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
>> +	[UBI3_CORE_CLAMP_ENABLE] = { 0x28A04, 8 },
>> +	[UBI2_CLKRST_CLAMP_ENABLE] = { 0x28A04, 7 },
>> +	[UBI2_CORE_CLAMP_ENABLE] = { 0x28A04, 6 },
>> +	[UBI1_CLKRST_CLAMP_ENABLE] = { 0x28A04, 5 },
>> +	[UBI1_CORE_CLAMP_ENABLE] = { 0x28A04, 4 },
>> +	[UBI0_CLKRST_CLAMP_ENABLE] = { 0x28A04, 3 },
>> +	[UBI0_CORE_CLAMP_ENABLE] = { 0x28A04, 2 },
>> +	[NSSNOC_NSS_CSR_ARES] = { 0x28A04, 1 },
>> +	[NSS_CSR_ARES]  { 0x28A04, 0 },
> 
> Hi Devi,
> 
> There appears to be an '=' missing in the line above.

Hi Simon,
Thanks for catching it! will update it in V2.

Regards,
Devi Priya
> 
> ...
Devi Priya July 18, 2023, 9:12 a.m. UTC | #3 
On 7/11/2023 3:26 PM, Krzysztof Kozlowski wrote:
> On 11/07/2023 11:35, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig         |    6 +
>>   drivers/clk/qcom/Makefile        |    1 +
>>   drivers/clk/qcom/nsscc-ipq9574.c | 3080 ++++++++++++++++++++++++++++++
>>   3 files changed, 3087 insertions(+)
>>   create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 263e55d75e3f..5556063d204f 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -195,6 +195,12 @@ config IPQ_GCC_9574
>>   	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>>   	  of ipq9574.
>>   
>> +config IPQ_NSSCC_9574
>> +	tristate "IPQ9574 NSS Clock Controller"
> 
> I think you do not run arm32 there, so missing depends on ARM64 ||
> COMPILE_TEST

Okay, will update this in V2

Thanks,
Devi Priya
> 
>> +	depends on IPQ_GCC_9574
>> +	help
>> +	  Support for NSS clock controller on ipq9574 devices.
>> +
> 
> 
> Best regards,
> Krzysztof
>
Devi Priya July 18, 2023, 9:13 a.m. UTC | #4 
On 7/11/2023 4:20 PM, Dmitry Baryshkov wrote:
> On 11/07/2023 12:35, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 
>> based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig         |    6 +
>>   drivers/clk/qcom/Makefile        |    1 +
>>   drivers/clk/qcom/nsscc-ipq9574.c | 3080 ++++++++++++++++++++++++++++++
>>   3 files changed, 3087 insertions(+)
>>   create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 263e55d75e3f..5556063d204f 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -195,6 +195,12 @@ config IPQ_GCC_9574
>>         i2c, USB, SD/eMMC, etc. Select this for the root clock
>>         of ipq9574.
>> +config IPQ_NSSCC_9574
>> +    tristate "IPQ9574 NSS Clock Controller"
>> +    depends on IPQ_GCC_9574
>> +    help
>> +      Support for NSS clock controller on ipq9574 devices.
>> +
>>   config MSM_GCC_8660
>>       tristate "MSM8660 Global Clock Controller"
>>       depends on ARM || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index e6e294274c35..8ba882186bff 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -29,6 +29,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>   obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>   obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>   obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>> +obj-$(CONFIG_IPQ_NSSCC_9574)    += nsscc-ipq9574.o
>>   obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>   obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>   obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c 
>> b/drivers/clk/qcom/nsscc-ipq9574.c
>> new file mode 100644
>> index 000000000000..b6bed0d24059
>> --- /dev/null
>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>> @@ -0,0 +1,3080 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/err.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-pll.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "common.h"
>> +#include "reset.h"
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> +    DT_BIAS_PLL_CC_CLK,
>> +    DT_BIAS_PLL_NSS_NOC_CLK,
>> +    DT_BIAS_PLL_UBI_NC_CLK,
>> +    DT_GCC_GPLL0_OUT_AUX,
>> +    DT_UNIPHY0_GCC_RX_CLK,
>> +    DT_UNIPHY0_GCC_TX_CLK,
>> +    DT_UNIPHY1_GCC_RX_CLK,
>> +    DT_UNIPHY1_GCC_TX_CLK,
>> +    DT_UNIPHY2_GCC_RX_CLK,
>> +    DT_UNIPHY2_GCC_TX_CLK,
>> +    DT_XO,
>> +};
>> +
>> +enum {
>> +    P_BIAS_PLL_CC_CLK,
>> +    P_BIAS_PLL_NSS_NOC_CLK,
>> +    P_BIAS_PLL_UBI_NC_CLK,
>> +    P_GCC_GPLL0_OUT_AUX,
>> +    P_UBI32_PLL_OUT_MAIN,
>> +    P_UNIPHY0_GCC_RX_CLK,
>> +    P_UNIPHY0_GCC_TX_CLK,
>> +    P_UNIPHY1_GCC_RX_CLK,
>> +    P_UNIPHY1_GCC_TX_CLK,
>> +    P_UNIPHY2_GCC_RX_CLK,
>> +    P_UNIPHY2_GCC_TX_CLK,
>> +    P_XO,
>> +};
>> +
>> +static const struct alpha_pll_config ubi32_pll_config = {
>> +    .l = 0x3e,
>> +    .alpha = 0x6666,
>> +    .config_ctl_val = 0x200d4aa8,
>> +    .config_ctl_hi_val = 0x3c,
>> +    .main_output_mask = BIT(0),
>> +    .aux_output_mask = BIT(1),
>> +    .pre_div_val = 0x0,
>> +    .pre_div_mask = BIT(12),
>> +    .post_div_val = 0x0,
>> +    .post_div_mask = GENMASK(9, 8),
>> +    .alpha_en_mask = BIT(24),
>> +    .test_ctl_val = 0x1c0000c0,
>> +    .test_ctl_hi_val = 0x4000,
>> +};
>> +
>> +static struct clk_alpha_pll ubi32_pll_main = {
>> +    .offset = 0x28000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> +    .flags = SUPPORTS_DYNAMIC_UPDATE,
>> +    .clkr = {
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "ubi32_pll_main",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_XO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_huayra_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>> +    .offset = 0x28000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> +    .width = 2,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "ubi32_pll",
>> +        .parent_hws = (const struct clk_hw *[]) {
>> +            &ubi32_pll_main.clkr.hw
>> +        },
>> +        .num_parents = 1,
>> +        .ops = &clk_alpha_pll_postdiv_ro_ops,
>> +        .flags = CLK_SET_RATE_PARENT,
>> +    },
>> +};
>> +
> 
> [skipped the rest, LGTM]
> 
>   +
>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>> +{
>> +    struct regmap *regmap;
>> +    struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>> +
>> +    regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>> +    if (IS_ERR(regmap))
>> +        return PTR_ERR(regmap);
>> +
>> +    /* SW Workaround for UBI Huayra PLL */
>> +    regmap_update_bits(regmap, 0x2800C, BIT(26), BIT(26));
> 
> Can we directly set the correct value via ubi32_pll_config.test_ctl_val ?

Sure, will check and update in V2
> 
>> +
>> +    clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
>> +
>> +    return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>> +}
>> +
>> +static struct platform_driver nss_cc_ipq9574_driver = {
>> +    .probe = nss_cc_ipq9574_probe,
>> +    .driver = {
>> +        .name = "qcom,nsscc-ipq9574",
>> +        .of_match_table = nss_cc_ipq9574_match_table,
>> +    },
>> +};
>> +
>> +static int __init nss_cc_ipq9574_init(void)
>> +{
>> +    return platform_driver_register(&nss_cc_ipq9574_driver);
>> +}
>> +subsys_initcall(nss_cc_ipq9574_init);
>> +
>> +static void __exit nss_cc_ipq9574_exit(void)
>> +{
>> +    platform_driver_unregister(&nss_cc_ipq9574_driver);
>> +}
>> +module_exit(nss_cc_ipq9574_exit);
> 
> module_platform_driver ?
okay

Thanks,
Devi Priya
> 
>> +
>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>> +MODULE_LICENSE("GPL");
>