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[0/4] IPQ8074 pcie/wcss fixes

Message ID 20230623093445.3977772-1-quic_srichara@quicinc.com
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Series IPQ8074 pcie/wcss fixes | expand

Message

Sricharan R June 23, 2023, 9:34 a.m. UTC 
These are required to have pcie/wcss working on IPQ8074 based
boards. Pcie was broken recently, first patch fixes that and
next 2 are for adding WCSS reset and 1 for adding reserved region
for NSS.

Will be following this up with few more dts updates and pcie
fixes.

Sricharan Ramabadhran (4):
  pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3
  dt-bindings: clock: qcom: Add reset for WCSSAON
  clk: qcom: Add WCSSAON reset
  dts: Reserve memory region for NSS and TZ

 arch/arm64/boot/dts/qcom/ipq8074.dtsi        | 7 ++++++-
 drivers/clk/qcom/gcc-ipq8074.c               | 1 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 2 +-
 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
 4 files changed, 9 insertions(+), 2 deletions(-)

Comments

Sricharan R June 30, 2023, 5:23 a.m. UTC | #1 
On 6/24/2023 12:04 PM, Manivannan Sadhasivam wrote:
> On Fri, Jun 23, 2023 at 03:04:41PM +0530, Sricharan Ramabadhran wrote:
>> These are required to have pcie/wcss working on IPQ8074 based
>> boards. Pcie was broken recently, first patch fixes that and
>> next 2 are for adding WCSS reset and 1 for adding reserved region
>> for NSS.
>>
>> Will be following this up with few more dts updates and pcie
>> fixes.
>>
> 
> Since there is no direct relation between pcie and clk patches, these should've
> been submitted separately.
> 

  ok, just grouped them as a miscellaneous. Will post the pcie fix
  separately.

Regards,
  Sricharan
Sricharan R June 30, 2023, 5:24 a.m. UTC | #2 
On 6/24/2023 12:02 PM, Manivannan Sadhasivam wrote:
> On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
>> pcie slave addr size was initially set to 0x358, but
>> was wrongly changed to 0x168 as a part of
>> 'PCI: qcom: Sort and group registers and bitfield definitions'
>> Fixing it back to right value here.
>>
>> Without this pcie bring up on IPQ8074 is broken now.
>>
> 
> Subject prefix should be: "PCI: qcom: "
> 
>> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
> 
> Fixes tag is referring to a wrong commit. Correct one is:
> 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
> 

  ok.

>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 4ab30892f6ef..59823beed13f 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -43,7 +43,7 @@
>>   #define PARF_PHY_REFCLK				0x4c
>>   #define PARF_CONFIG_BITS			0x50
>>   #define PARF_DBI_BASE_ADDR			0x168
>> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
>> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
> 
> You should just remove PARF_SLV_ADDR_SPACE_SIZE_2_3_3 and use
> PARF_SLV_ADDR_SPACE_SIZE which already has the value of 0x358.
> 

  ok

Regards,
  Sricharan