| Message ID | 20230525122930.17141-1-srinivas.kandagatla@linaro.org |
|---|---|
| Headers | show |
| Series | clk: qcom: sc8280xp: add lpasscc reset control | expand |
Resending as my previous email probably got lost. If you got it twice, apologies. On 25/05/2023 14:29, Srinivas Kandagatla wrote: > Add support for the lpass clock controller found on SC8280XP based devices. > This would allow lpass peripheral loader drivers to control the clocks and > bring the subsystems out of reset. > > Currently this patch only supports resets as the Q6DSP is in control of > LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg > channel. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > --- > drivers/clk/qcom/Kconfig | 8 ++++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/lpasscc-sc8280xp.c | 63 +++++++++++++++++++++++++++++ > 3 files changed, 72 insertions(+) > create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 85869e7a9f16..e25993abb519 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -523,6 +523,14 @@ config SC_LPASSCC_7280 > Say Y if you want to use the LPASS branch clocks of the LPASS clock > controller to reset the LPASS subsystem. > > +config SC_LPASSCC_8280XP > + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST Best regards, Krzysztof
On 31/05/2023 21:01, Krzysztof Kozlowski wrote: > On 25/05/2023 14:29, Srinivas Kandagatla wrote: >> Add support for the lpass clock controller found on SC8280XP based devices. >> This would allow lpass peripheral loader drivers to control the clocks and >> bring the subsystems out of reset. >> >> Currently this patch only supports resets as the Q6DSP is in control of >> LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg >> channel. >> >> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> --- >> drivers/clk/qcom/Kconfig | 8 ++++ >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/lpasscc-sc8280xp.c | 63 +++++++++++++++++++++++++++++ >> 3 files changed, 72 insertions(+) >> create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 85869e7a9f16..e25993abb519 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -523,6 +523,14 @@ config SC_LPASSCC_7280 >> Say Y if you want to use the LPASS branch clocks of the LPASS clock >> controller to reset the LPASS subsystem. >> >> +config SC_LPASSCC_8280XP >> + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" > > depends on ARM64 || COMPILE_TEST Thanks, Will do that in v3. --srini > > Best regards, > Krzysztof >
On 31/05/2023 21:03, Krzysztof Kozlowski wrote: > On 25/05/2023 14:29, Srinivas Kandagatla wrote: >> Soundwire controllers on sc8280xp needs an explicit reset, add >> support for this. >> >> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> index 6730349e34f4..39be2e89ce05 100644 >> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi >> @@ -6,6 +6,7 @@ >> >> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> >> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> >> +#include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/interconnect/qcom,osm-l3.h> >> #include <dt-bindings/interconnect/qcom,sc8280xp.h> >> @@ -2560,6 +2561,8 @@ >> interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; >> clocks = <&rxmacro>; >> clock-names = "iface"; >> + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; >> + reset-names = "swr_audio_cgcr"; >> label = "RX"; >> >> qcom,din-ports = <0>; >> @@ -2634,6 +2637,8 @@ >> interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; >> clocks = <&wsamacro>; >> clock-names = "iface"; >> + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; >> + reset-names = "swr_audio_cgcr"; >> label = "WSA"; >> >> qcom,din-ports = <2>; >> @@ -2656,6 +2661,14 @@ >> status = "disabled"; >> }; >> >> + lpass_audiocc: clock-controller@32a9000 { >> + compatible = "qcom,sc8280xp-lpassaudiocc"; >> + reg = <0 0x032a9000 0 0x1000>; >> + qcom,adsp-pil-mode; > > Here and... > >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> swr2: soundwire-controller@3330000 { >> compatible = "qcom,soundwire-v1.6.0"; >> reg = <0 0x03330000 0 0x2000>; >> @@ -2665,6 +2678,8 @@ >> >> clocks = <&txmacro>; >> clock-names = "iface"; >> + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; >> + reset-names = "swr_audio_cgcr"; >> label = "TX"; >> #sound-dai-cells = <1>; >> #address-cells = <2>; >> @@ -2901,6 +2916,14 @@ >> }; >> }; >> >> + lpasscc: clock-controller@33e0000 { >> + compatible = "qcom,sc8280xp-lpasscc"; >> + reg = <0 0x033e0000 0 0x12000>; >> + qcom,adsp-pil-mode; > > ... here - where do you use these properties? Driver ignores them. Wil add a check in driver. > > AFAIR, these were only for sc7280 where we supported two variants for audio. > we can drop this property altogether, But having this flag will make sure that the bindings are in a ready state to accommodate a new variant of sc8280xp with dsp bypass. --srini > Best regards, > Krzysztof >
On SC8280XP, LPASS IP is controlled by q6dsp, however the reset lines required by some of the IPs like Soundwire still need to be programmed from Apps processor. This patchset adds support to reset controller on LPASS CC and LPASS AudioCC. Tested on X13s. Thanks, Srini Changes since v1: - updated dt binding to be in a accending order and fixed spaces in example - updated kconfig and make file to fix the order. - updated driver with various minor comments Johan. - added defconfig changes patch - fixed missing reset entry for swr0 Srinivas Kandagatla (6): dt-bindings: clock: Add YAML schemas for LPASSCC and reset on SC8280XP dt-bindings: clock: Add YAML schemas for LPASS AUDIOCC and reset on SC8280XP clk: qcom: Add lpass clock controller driver for SC8280XP clk: qcom: Add lpass audio clock controller driver for SC8280XP arm64: dts: qcom: sc8280xp: add resets for soundwire controllers arm64: defconfig: Enable sc828x0xp lpasscc clock controller .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 68 +++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 23 +++++ arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc8280xp.c | 86 +++++++++++++++++++ .../dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 17 ++++ 7 files changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c create mode 100644 include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h