From patchwork Wed May 17 06:24:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 683046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8523C77B7D for ; Wed, 17 May 2023 06:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232667AbjEQGYi (ORCPT ); Wed, 17 May 2023 02:24:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232670AbjEQGYc (ORCPT ); Wed, 17 May 2023 02:24:32 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6817D3586 for ; Tue, 16 May 2023 23:24:30 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-24dfc3c662eso357341a91.3 for ; Tue, 16 May 2023 23:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684304670; x=1686896670; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6xI3hUbCW+FwBwOTtLOPQqL67ArdQOyuoW/lXxNMjQ4=; b=TjIOj1nxjzJLlVoNwu90CZ1Y7QDf9vJ3j9fmZdGp/f5B+A7/VApd9RRGZN2yRj1SFx Chx+iKhybZ/WOnhRRBFc/ZVJImxF1/nFkumey7JukfAfkzlYWYBVUBySfZQ+gSUcaDB3 Iczqs2/QELdaztltVlzQHhj4CYPe0nj/yZL6a9sqY+B4/lKwVYSDLex1NkDwthxevCrn fkxxXO/EcUhKBS+EUafD/mQ6+A6QoKAetJoii6Ob+64/atgfC4fh7iRnB0KMnYb5GtU5 OL0N86zMpy+PG3/ntLVUbKUGDX3M9AS2GlJ8SbGxZCyCoVx5CVQSUi6jUYQiSthTr7b/ Riew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684304670; x=1686896670; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6xI3hUbCW+FwBwOTtLOPQqL67ArdQOyuoW/lXxNMjQ4=; b=JdGgOmCFyZ986wz/SIAymWF4NEBY7FHBkOaq9XdZBhPSXBfWXEDNTlL2UOsLvWJLHN SYcquRj2tjnsarrXFFilfVHviWoerHoT0vwGRdbJaaCtW3DRxa+eZv5REkul1xuoSQN7 48nwwpCyV6xSq4KJc6qpHmOvxjKW1YZEnyEc0G2SiTcSN+Qt+04jfY98NR+8rIBeNSEx lnI7YNGscFxGIeFbbrKRYh01tY+PJZW4K0v7EHqWMcutOvewTLpSbQo/eGK6m/ZnZ6/o wbDu5nQ3mSEguz/7FrWN+SOuw6l6MpMkyhcJ4j3Qv0R5n9eUSrj/H0qW6oib+O/X3FPj slIA== X-Gm-Message-State: AC+VfDwWrf6gUVwoAW/t+dwcXYR5Tc9Ts3RQmEMoQKcjI/wmqxnQmHfx 0oGyVE9qK1LiNSkhPIl1Hiq2 X-Google-Smtp-Source: ACHHUZ6bDqUMdz7zLfRy8rwKL/pK9Dv4oR14RRfhpSlxq+QKBxvIZ7pOILsD7PldWRxwGTi5sAPKgA== X-Received: by 2002:a17:90a:6b43:b0:253:3ca1:4b8c with SMTP id x3-20020a17090a6b4300b002533ca14b8cmr2178520pjl.4.1684304669737; Tue, 16 May 2023 23:24:29 -0700 (PDT) Received: from localhost.localdomain ([59.92.102.59]) by smtp.gmail.com with ESMTPSA id z22-20020a17090acb1600b002508f0ac3edsm693282pjt.53.2023.05.16.23.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 23:24:29 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v7 0/2] Fix crash when using Qcom LLCC/EDAC drivers Date: Wed, 17 May 2023 11:54:18 +0530 Message-Id: <20230517062421.56970-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hello, This series fixes the crash seen on the Qualcomm SM8450 chipset with the LLCC/EDAC drivers. The problem was due to the Qcom EDAC driver using the fixed LLCC register offsets for detecting the LLCC errors. This seems to have worked for SoCs till SM8450. But in SM8450, the LLCC register offsets were changed. So accessing the fixed offsets causes the crash on this platform. So for fixing this issue, and also to make it work on future SoCs, let's pass the LLCC offsets from the Qcom LLCC driver based on the individual SoCs and let the EDAC driver make use of them. This series has been tested on SM8450 based dev board. Thanks, Mani [1] https://lore.kernel.org/linux-arm-msm/20230314053725.13623-1-manivannan.sadhasivam@linaro.org/ Changes in v7: * Rebased on top of v6.4-rc1 Changes in v6: * Rebased on top of v6.3-rc1 * Dropped the Kconfig patch that got applied Changes in v5: * Added fixes tag and CCed stable mentioning the dependency * Added a patch to fix the build error with COMPILE_TEST Changes in v4: * Dropped the patches that were already applied * Rebased on top of v6.1-rc5 Changes in v3: * Instead of using SoC specific register offset naming convention, used LLCC version based as suggested by Sai * Fixed the existing reg_offset naming convention to clearly represent the LLCC version from which the offsets were changed * Added Sai's Acked-by to MAINTAINERS patch * Added a new patch that removes an extra error no assignment Changes in v2: * Volunteered myself as a maintainer for the EDAC driver since the current maintainers have left Qualcomm and I couldn't get hold of them. Manivannan Sadhasivam (2): EDAC/qcom: Remove extra error no assignment in qcom_llcc_core_setup() EDAC/qcom: Get rid of hardcoded register offsets drivers/edac/qcom_edac.c | 119 ++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 6 -- 2 files changed, 59 insertions(+), 66 deletions(-)