| Message ID | 20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org |
|---|---|
| Headers | show |
| Series | Adreno QoL changes | expand |
On Fri, May 19, 2023 at 6:29 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > We have the necessary information, so explain which bit does what. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 9fb214f150dd..deed42675fe2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -771,9 +771,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > } > > /* > - * Enable access protection to privileged registers, fault on an access > - * protect violation and select the last span to protect from the start > - * address all the way to the end of the register address space > + * BIT(0) - Enable access protection to privileged registers > + * BIT(1) - Enable fault on an access protect violation > + * BIT(3) - Select the last span to protect from the start > + * address all the way to the end of the register address space Even better would be to give these bitfields names in the xml, which also gets you more meaningful decoding. We've been better about not open-coding a lot of stuff on the mesa side, but it is a bit easier with header generation integrated into the build.. but less open-coding on the kernel side is still a noble goal BR, -R > */ > gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); > > > -- > 2.40.1 >
This series brings some niceties in preparation for A7xx introduction. It should be fully independent of the GMU wrapper series. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Changes in v2: - Drop switching to using the GMU_AO counter in timestamp - Add a definition for REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, may be subbed with a register sync after mesa MR22901 - Link to v1: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v1-0-7a964f2e99c2@linaro.org --- Konrad Dybcio (6): drm/msm/a6xx: Add REG_A6XX_GMU_AHB_FENCE_STATUS_CLR definition drm/msm/a6xx: Explain CP_PROTECT_CNTL writes in a6xx_set_cp_protect drm/msm/a6xx: Skip empty protection ranges entries drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start drm/msm/a6xx: Improve GMU force shutdown sequence drm/msm/a6xx: Fix up GMU region reservations drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++++++++----- 3 files changed, 28 insertions(+), 9 deletions(-) --- base-commit: dbd91ef4e91c1ce3a24429f5fb3876b7a0306733 change-id: 20230517-topic-a7xx_prep-787a69c7d0ff Best regards,