From patchwork Fri Apr 7 10:50:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 671586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9605C77B61 for ; Fri, 7 Apr 2023 10:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240619AbjDGKuq (ORCPT ); Fri, 7 Apr 2023 06:50:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240622AbjDGKun (ORCPT ); Fri, 7 Apr 2023 06:50:43 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32D41A273 for ; Fri, 7 Apr 2023 03:50:41 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id he13so4231204wmb.2 for ; Fri, 07 Apr 2023 03:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680864639; x=1683456639; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=06TnYBdo9T2x70dl6lUY38eRXb4b9fDtFg6W0E/jF9s=; b=wYDrtmyCUeuPHoQ+a+L+bYIKD5tVHF0T4I7wDqd7k8R9pfkM+J9OhoQDyESXnzz1iz k3ooh1VU2Q8gW2TSMLRlbtghkI19sy19ypdWoc+Omxxem6YZuXrgCPFr2LGsUITxWliE +zBT3kCgH6wuumOU7JtR9EXz8g2jSMCePAMrqaI2lCCSey7kNVinVsK5dKZLfyxYqxVp gySoNb8rDY/w1WGiu9q8a23DHmXgXkXf7veY050tTyaiF3nf+/mROPMw7MS6i60JLSEW pbhVwVkWGBoCGj+2wJv+zy42hiGSIYRliEDZRZysa98BQX7OD7u+MFN7XB7Gr72FM0OU A2QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680864639; x=1683456639; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=06TnYBdo9T2x70dl6lUY38eRXb4b9fDtFg6W0E/jF9s=; b=2hmAUd2Id2e7dqRQGECcn1HusQh8ttYvnv3CO/aLCY7+OI9o0dCHq/N1RqWTOfKUPw cfhOB/CZB1qi0aWnprucitV/memoJdRrK0zG/O2g7KvbBduSEB7yEQzhCSw9t0q5no/P h2HE0hXTqasb8K7B9pVQmURNH+0RbLgtcNzPcrtp0s3uxQkmgSa0z5wFCZ0Kx2Vfm+l4 kpn4frUZM167dxgp1qjRAX0C4eBmJuwufwz0c9+XGRkRC91UGpsgL616YgLoZ2IOq1kS 643FNaLudn+fo5Qh5ncwfkvwJ3cW46eCwrYyQZGQR3HsgePseFBHnk7WLVpzuQ2BC4VH 1O/Q== X-Gm-Message-State: AAQBX9flS0QuKClbLGq7I14odobEsXOU0pTW8gIliAKZGg6SWXz8BTqE t3ptLT5BjKqlUTps7SFHn1zJGA== X-Google-Smtp-Source: AKy350ZwCtSoQjiiwA1Djng0xz4M3/ZbNCZlAcTQ8nHuWoyebrI7lbwqlVuy6DqJem2lF9sXrcoJ7A== X-Received: by 2002:a05:600c:2285:b0:3ee:ed5:6115 with SMTP id 5-20020a05600c228500b003ee0ed56115mr1076006wmf.19.1680864639120; Fri, 07 Apr 2023 03:50:39 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id i16-20020a05600c355000b003ede6540190sm8131909wmq.0.2023.04.07.03.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 03:50:38 -0700 (PDT) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" , Herbert Xu , "David S . Miller" , Eric Biggers Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v6 0/6] Add dedicated Qcom ICE driver Date: Fri, 7 Apr 2023 13:50:23 +0300 Message-Id: <20230407105029.2274111-1-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As both SDCC and UFS drivers use the ICE with duplicated implementation, while none of the currently supported platforms make use concomitantly of the same ICE IP block instance, the new SM8550 allows both UFS and SDCC to do so. In order to support such scenario, there is a need for a unified implementation and a devicetree node to be shared between both types of storage devices. So lets drop the duplicate implementation of the ICE from both SDCC and UFS and make it a dedicated (soc) driver. For now, only SM8550 has been added to support the new approach. This also involves adding support for HW version 4.x. The v5 is here: https://lore.kernel.org/all/20230403200530.2103099-1-abel.vesa@linaro.org/ Changes since v5: * See each individual patch for changelogs. Changes since v4: * dropped the SDHCI dt-bindings patch as it will be added along with the first use of qcom,ice property from an SDHCI DT node Abel Vesa (6): dt-bindings: crypto: Add Qualcomm Inline Crypto Engine dt-bindings: ufs: qcom: Add ICE phandle soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver scsi: ufs: ufs-qcom: Switch to the new ICE API mmc: sdhci-msm: Switch to the new ICE API arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node .../crypto/qcom,inline-crypto-engine.yaml | 42 ++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 + drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/sdhci-msm.c | 223 +++-------- drivers/soc/qcom/Kconfig | 4 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ice.c | 366 ++++++++++++++++++ drivers/ufs/host/Kconfig | 2 +- drivers/ufs/host/Makefile | 4 +- drivers/ufs/host/ufs-qcom-ice.c | 244 ------------ drivers/ufs/host/ufs-qcom.c | 99 ++++- drivers/ufs/host/ufs-qcom.h | 32 +- include/soc/qcom/ice.h | 37 ++ 14 files changed, 637 insertions(+), 454 deletions(-) create mode 100644 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml create mode 100644 drivers/soc/qcom/ice.c delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c create mode 100644 include/soc/qcom/ice.h