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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id cb8-20020a170906a44800b009fd4583851esm3569253ejb.178.2023.11.25.06.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:27:12 -0800 (PST) From: Konrad Dybcio Subject: [PATCH v6 0/2] Resolve MPM register space situation Date: Sat, 25 Nov 2023 15:27:02 +0100 Message-Id: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIADYEYmUC/4XQS2rEMBAE0KsMWkdBbn09q9wjhCDJLVvgH9LEJ Ay+e3pmFwzxsgr6FfSdVSwZK7te7qzglmteZgrm5cLi4Oceee4oMxAghQTHb8uaI59qX/z0Oa0 Tj8a5gDJEaBWjs+Ar8lD8HAc6nL/Gkcq1YMrfz533D8pDrrel/Dxnt+bR/rOwNVzwJljnvE7aS /k25tmX5XUpPXtoG5wJQAKC8sqhtkl0B0GeCZIEiBYS2KCsMAdBnQmKhOBROuiiSC0cBH0maBI MCgP0itYE/UfY9/0XObyPGs4BAAA= To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700922431; l=2638; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0I8R25SRzKeRrQMqe0fAK3J+H2k5tsTdUqt2Uq5RJHU=; b=QFsXLnXIMN1IoCnqikWluUY14tvflsxnkWb8phLjcUqBiUXspGAGLvVysCH0QESP7XLOpVo1G 4esWS6EyJL3CY2k1JE0MutJFaTtBVd/VbKDAXI5WzsUNV6Kx8r2qlXt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= v5 -> v6: - Resending due to no responses. - Change of base to next-20231124 (no changes to the patch) Link to v5: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v5-0-6e06278896b5@linaro.org v4 -> v5: - Pick up tags - Rebase on Rob's of_ header untanglement Link to v4: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v4-0-bae382dc0f92@linaro.org v3 -> v4: - Fix up indentation in the bindings patch - Add an example glink-edge subnode to remoteproc-rpm (its bindings require that..) Link to v3: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v3-0-2c72f27b4706@linaro.org v2 -> v3: - Fix the example - Pick up tags - remove the outdated example from the cover letter, check bindings should you want to see one The bindings for the wrapper node used in the yaml example are merged in qcom/for-next Link to v2: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org v1 -> v2: - deprecate 'reg', make qcom,rpm-msg-ram required [1/2] - Use devm_ioremap() [2/2] Link to v1: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org Depends on resolution of https://github.com/devicetree-org/dt-schema/issues/104 The MPM (and some other things, irrelevant to this patchset) resides (as far as the ARM cores are concerned, anyway) in a MMIO-mapped region that's a portion of the RPM (low-power management core)'s RAM, known as the RPM Message RAM. Representing this relation in the Device Tree creates some challenges, as one would either have to treat a memory region as a bus, map nodes in a way such that their reg-s would be overlapping, or supply the nodes with a slice of that region. This series implements the third option, by adding a qcom,rpm-msg-ram property, which has been used for some drivers poking into this region before. Bindings ABI compatibility is preserved through keeping the "normal" (a.k.a read the reg property and map that region) way of passing the register space. Signed-off-by: Konrad Dybcio --- Konrad Dybcio (2): dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++------- drivers/irqchip/irq-qcom-mpm.c | 21 +++++++-- 2 files changed, 53 insertions(+), 20 deletions(-) --- base-commit: 8c9660f6515396aba78d1168d2e17951d653ebf2 change-id: 20230328-topic-msgram_mpm-c688be3bc294 Best regards,