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[83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:29 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio Subject: [PATCH v5 00/10] SM6(11|12|37)5 GPUCC Date: Wed, 1 Feb 2023 19:36:16 +0100 Message-Id: <20230201183626.351211-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This series brings GPUCC support and the correlated bindings for three midrange SoCs, all of which host a GMU-less A6xx GPU. v5 fixes some issues pointed out by Dmitry and picks up tags v4: https://lore.kernel.org/linux-arm-msm/20230130235926.2419776-1-konrad.dybcio@linaro.org/ v4 only brings a tiny bindings amend to [7/8].. I thought I could fix it without running dt_binding_check but oh was I humbled again.. v3: https://lore.kernel.org/linux-arm-msm/20230130153252.2310882-1-konrad.dybcio@linaro.org/T/#t Konrad Dybcio (10): clk: qcom: branch: Add helper functions for setting retain bits clk: qcom: branch: Add helper functions for setting SLEEP/WAKE bits clk: qcom: branch: Move CBCR bits definitions to the header file clk: qcom: branch: Clean up branch enable registers dt-bindings: clock: Add Qcom SM6125 GPUCC clk: qcom: Add GPU clock controller driver for SM6125 dt-bindings: clock: Add Qcom SM6375 GPUCC clk: qcom: Add GPU clock controller driver for SM6375 dt-bindings: clock: Add Qcom SM6115 GPUCC clk: qcom: Add GPU clock controller driver for SM6115 .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 ++ .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++ .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++ drivers/clk/qcom/Kconfig | 27 + drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/clk-branch.c | 15 +- drivers/clk/qcom/clk-branch.h | 43 ++ drivers/clk/qcom/gpucc-sm6115.c | 503 ++++++++++++++++++ drivers/clk/qcom/gpucc-sm6125.c | 424 +++++++++++++++ drivers/clk/qcom/gpucc-sm6375.c | 469 ++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 ++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 ++ 13 files changed, 1759 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 drivers/clk/qcom/gpucc-sm6115.c create mode 100644 drivers/clk/qcom/gpucc-sm6125.c create mode 100644 drivers/clk/qcom/gpucc-sm6375.c create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h