| Message ID | 20230102105821.28243-1-manivannan.sadhasivam@linaro.org |
|---|---|
| Headers | show |
| Series | Qcom: Add GIC-ITS support to SM8450 PCIe controllers | expand |
On 2.01.2023 11:58, Manivannan Sadhasivam wrote: > Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs > received from endpoint devices to the CPU using GIC-ITS MSI controller. > Add support for it. > > Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the > msi-map-mask of 0xff00, all the 32 devices under these two busses can > share the same Device ID. > > The GIC-ITS MSI implementation provides an advantage over internal MSI > implementation using Locality-specific Peripheral Interrupts (LPI) that > would allow MSIs to be targeted for each CPU core. > > It should be noted that the MSIs for BDF (1:0.0) only works with Device > ID of 0x5980 and 0x5a00. Hence, the IDs are swapped. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # Xperia 1 IV (WCN6855) Konrad > arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 570475040d95..c4dd5838fac6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1733,9 +1733,13 @@ pcie0: pci@1c00000 { > ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, > <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; > > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi"; > - #interrupt-cells = <1>; > + /* > + * MSIs for BDF (1:0.0) only works with Device ID 0x5980. > + * Hence, the IDs are swapped. > + */ > + msi-map = <0x0 &gic_its 0x5981 0x1>, > + <0x100 &gic_its 0x5980 0x1>; > + msi-map-mask = <0xff00>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > @@ -1842,9 +1846,13 @@ pcie1: pci@1c08000 { > ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, > <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; > > - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi"; > - #interrupt-cells = <1>; > + /* > + * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. > + * Hence, the IDs are swapped. > + */ > + msi-map = <0x0 &gic_its 0x5a01 0x1>, > + <0x100 &gic_its 0x5a00 0x1>; > + msi-map-mask = <0xff00>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
On Mon, Jan 02, 2023 at 04:28:19PM +0530, Manivannan Sadhasivam wrote: > Stanimir has left mm-sol and already expressed his wish to not continue > maintaining the PCIe RC driver. So his entry can be removed. > > Adding myself as the co-maintainer since I took over the PCIe RC driver > maintainership from Stanimir. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Bjorn Andersson <andersson@kernel.org> Regards, Bjorn > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index a5859bb3dc28..a3639920fcbb 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex > > maintainers: > - Bjorn Andersson <bjorn.andersson@linaro.org> > - - Stanimir Varbanov <svarbanov@mm-sol.com> > + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > description: | > Qualcomm PCIe root complex controller is based on the Synopsys DesignWare > -- > 2.25.1 >