| Message ID | 20221110151748.795767-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | phy: qcom-qmp-ufs: add symbol clocks support | expand |
On 10/11/2022 16:17, Dmitry Baryshkov wrote: > Add #clock-cells property to the QMP UFS PHYs to describe them as clock > providers. The QMP PHY provides rx and tx symbol clocks for the GCC. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml | 3 +++ > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 3 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 10/11/2022 16:17, Dmitry Baryshkov wrote: > Move the sleep_clk to make sure the gcc device node follows the schema. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index d32f08df743d..efb01fefe9c7 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -720,13 +720,13 @@ gcc: clock-controller@100000 { > #reset-cells = <1>; > #power-domain-cells = <1>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > <&pcie0_lane>, > - <&pcie1_lane>, > - <&sleep_clk>; > + <&pcie1_lane>; > clock-names = "bi_tcxo", > + "sleep_clk", > "pcie_0_pipe_clk", > - "pcie_1_pipe_clk", > - "sleep_clk"; > + "pcie_1_pipe_clk"; > }; > > gpi_dma2: dma-controller@800000 {
On 10/11/2022 16:17, Dmitry Baryshkov wrote: > Remove manually created symbol clocks and replace them with clocks > provided by PHY. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Maybe it would be worth exporting some #defines for these incides so that it's less likely for the next person referencing these DTs to make a mistake, but that could be done in a separate patch. Something similar could probably be useful for DSI BYTE/PIXEL clk Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 ++++- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 ++++--------------------- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 15 +++++++++++++-- > 3 files changed, 21 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index c0a2baffa49d..935ba6e6bc15 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -699,7 +699,9 @@ gcc: clock-controller@300000 { > <&pciephy_1>, > <&pciephy_2>, > <&ssusb_phy_0>, > - <0>, <0>, <0>; > + <&ufsphy_lane 0>, > + <&ufsphy_lane 1>, > + <&ufsphy_lane 2>; > clock-names = "cxo", > "cxo2", > "sleep_clk", > @@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 { > reg = <0x627400 0x12c>, > <0x627600 0x200>, > <0x627c00 0x1b4>; > + #clock-cells = <1>; > #phy-cells = <0>; > }; > }; > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 90a26f406bf3..51ca006dc5c1 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -37,24 +37,6 @@ sleep_clk: sleep-clk { > clock-frequency = <32000>; > #clock-cells = <0>; > }; > - > - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { > - compatible = "fixed-clock"; > - clock-frequency = <1000>; > - #clock-cells = <0>; > - }; > - > - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { > - compatible = "fixed-clock"; > - clock-frequency = <1000>; > - #clock-cells = <0>; > - }; > - > - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { > - compatible = "fixed-clock"; > - clock-frequency = <1000>; > - #clock-cells = <0>; > - }; > }; > > cpus { > @@ -661,9 +643,9 @@ gcc: clock-controller@100000 { > <0>, > <0>, > <0>, > - <&ufs_phy_rx_symbol_0_clk>, > - <&ufs_phy_rx_symbol_1_clk>, > - <&ufs_phy_tx_symbol_0_clk>, > + <&ufs_mem_phy_lanes 0>, > + <&ufs_mem_phy_lanes 1>, > + <&ufs_mem_phy_lanes 2>, > <0>, > <0>; > }; > @@ -2389,6 +2371,7 @@ ufs_mem_phy_lanes: phy@1d87400 { > <0 0x01d87c00 0 0x1dc>, > <0 0x01d87800 0 0x108>, > <0 0x01d87a00 0 0x1e0>; > + #clock-cells = <1>; > #phy-cells = <0>; > }; > }; > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index efb01fefe9c7..95c01391972a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -722,11 +722,21 @@ gcc: clock-controller@100000 { > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&sleep_clk>, > <&pcie0_lane>, > - <&pcie1_lane>; > + <&pcie1_lane>, > + <0>, > + <&ufs_mem_phy_lanes 0>, > + <&ufs_mem_phy_lanes 1>, > + <&ufs_mem_phy_lanes 2>, > + <0>; > clock-names = "bi_tcxo", > "sleep_clk", > "pcie_0_pipe_clk", > - "pcie_1_pipe_clk"; > + "pcie_1_pipe_clk", > + "pcie_1_phy_aux_clk", > + "ufs_phy_rx_symbol_0_clk", > + "ufs_phy_rx_symbol_1_clk", > + "ufs_phy_tx_symbol_0_clk", > + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; > }; > > gpi_dma2: dma-controller@800000 { > @@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 { > <0 0x01d87c00 0 0x1dc>, > <0 0x01d87800 0 0x108>, > <0 0x01d87a00 0 0x1e0>; > + #clock-cells = <1>; > #phy-cells = <0>; > }; > };