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[V4,0/3] PCI: designware-ep: Fix DBI access before core init

Message ID 20220919183342.4090-1-vidyas@nvidia.com
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Series PCI: designware-ep: Fix DBI access before core init | expand

Message

Vidya Sagar Sept. 19, 2022, 6:33 p.m. UTC 
This series attempts to fix the issue with core register (Ex:- DBI) accesses
causing system hang issues in platforms where there is a dependency on the
availability of PCIe Reference clock from the host for their core
initialization.
This series is verified on Tegra194 & Tegra234 platforms.

Manivannan, could you please verify on qcom platforms?

V4:
* Addressed review comments from Bjorn and Manivannan
* Added .ep_init_late() ops
* Added patches to refactor code in qcom and tegra platforms

Vidya Sagar (3):
  PCI: designware-ep: Fix DBI access before core init
  PCI: qcom-ep: Refactor EP initialization completion
  PCI: tegra194: Refactor EP initialization completion

 .../pci/controller/dwc/pcie-designware-ep.c   | 112 ++++++++++--------
 drivers/pci/controller/dwc/pcie-designware.h  |  10 +-
 drivers/pci/controller/dwc/pcie-qcom-ep.c     |  27 +++--
 drivers/pci/controller/dwc/pcie-tegra194.c    |   4 +-
 4 files changed, 85 insertions(+), 68 deletions(-)