[v2,0/7] Add PCIe support for SM8150 SoC

Changes since v1:
-----------------
- v1 can be found here: https://lore.kernel.org/linux-arm-msm/20220223192946.473172-1-bhupesh.sharma@linaro.org/T/
- Collected ACKs on [PATCH 1/7], [PATCH 2/7] and [PATCH 4/7] from Rob
  and Dmitry.
- Broke down another separately sent out PATCH (see [1]), into a 3 patches (one each for emac, pci
  and ufs gdsc defines) - one of which is carried as [PATCH 3/7]
  in this series, which fixes a compilation error.
  The rest of the gdsc defines have been sent out as separate patch(es).
[1]. https://patchwork.kernel.org/project/netdevbpf/patch/20220126221725.710167-4-bhupesh.sharma@linaro.org/
- Rob's bot reported a number of 'dtbs_check' errors with the v1 series,
  which are been fixed with a separate series now (see [2]), to ease the
  review of this series.
[2]. https://lore.kernel.org/linux-arm-msm/20220228123019.382037-1-bhupesh.sharma@linaro.org/T/


This series adds PCIe support for Qualcomm SM8150 SoC with relevant PHYs.
There are 2 PCIe instances on this SoC each with different PHYs. The PCIe
controller and PHYs are mostly compatible with the ones found on SM8250
SoC, hence the old drivers are modified to add the support.

This series has been tested on SA8155p ADP board with QCA6696 chipset connected
onboard.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>

Bhupesh Sharma (7):
  dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC
  dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings
  clk: qcom: gcc: Add PCIE_0_GDSC and PCIE_1_GDSC for SM8150
  phy: qcom-qmp: Add SM8150 PCIe QMP PHYs
  PCI: qcom: Add SM8150 SoC support
  arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
  arm64: dts: qcom: sa8155: Enable pcie nodes

 .../devicetree/bindings/pci/qcom,pcie.txt     |   5 +-
 .../devicetree/bindings/phy/qcom,qmp-phy.yaml |   4 +
 arch/arm64/boot/dts/qcom/sa8155p-adp.dts      |  42 +++
 arch/arm64/boot/dts/qcom/sm8150.dtsi          | 243 ++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c        |  16 ++
 drivers/phy/qualcomm/phy-qcom-qmp.c           |  90 +++++++
 include/dt-bindings/clock/qcom,gcc-sm8150.h   |   2 +
 7 files changed, 400 insertions(+), 2 deletions(-)

Hi Dmitry,

On Tue, 1 Mar 2022 at 17:13, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 01/03/2022 10:25, Bhupesh Sharma wrote:
> > The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
> > SM8250. Hence the support is added reusing the members of ops_2_7_0.
> >
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
> >   1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index c19cd506ed3f..66fbc0234888 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
> >       .config_sid = qcom_pcie_config_sid_sm8250,
> >   };
> >
> > +/* Qcom IP rev.: 1.5.0 */
> > +static const struct qcom_pcie_ops ops_1_5_0 = {
> > +     .get_resources = qcom_pcie_get_resources_2_7_0,
> > +     .init = qcom_pcie_init_2_7_0,
> > +     .deinit = qcom_pcie_deinit_2_7_0,
> > +     .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> > +     .post_init = qcom_pcie_post_init_2_7_0,
> > +     .post_deinit = qcom_pcie_post_deinit_2_7_0,
> > +     .config_sid = qcom_pcie_config_sid_sm8250,
> > +};
> > +
>
> This duplicates the ops_1_9_0, doesn't it?
> I'd suggest to reuse 1.9.0 structure and add a comment that it's also
> used for 1.5.0.

Ack. I will fix this in v3.

Regards,
Bhupesh

> >   static const struct qcom_pcie_cfg apq8084_cfg = {
> >       .ops = &ops_1_0_0,
> >   };
> > @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
> >       .ops = &ops_2_7_0,
> >   };
> >
> > +static const struct qcom_pcie_cfg sm8150_cfg = {
> > +     .ops = &ops_1_5_0,
> > +};
> > +
> >   static const struct qcom_pcie_cfg sm8250_cfg = {
> >       .ops = &ops_1_9_0,
> >   };
> > @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> >       { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
> >       { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
> >       { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
> > +     { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
> >       { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
> >       { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
> >       { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
>
>
> --
> With best wishes
> Dmitry