| Message ID | 20210331105735.3690009-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | drm/msm/dsi: refactor MSM DSI PHY/PLL drivers | expand |
On 2021-03-31 03:57, Dmitry Baryshkov wrote: > Make save_state/restore callbacks accept struct msm_dsi_phy rather than > struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing > us to drop struct msm_dsi_pll_ops. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 12 +++---- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++--- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 24 ++++++------- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 24 ++++++------- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 34 ++++++++----------- > .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 18 +++++----- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 24 ++++++------- > 7 files changed, 64 insertions(+), 83 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index a1360e2dad3b..2c5ccead3baa 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -858,9 +858,9 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy > *phy, > > void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy) > { > - if (phy->cfg->pll_ops.save_state) { > - phy->cfg->pll_ops.save_state(phy->pll); > - phy->pll->state_saved = true; > + if (phy->cfg->ops.save_pll_state) { > + phy->cfg->ops.save_pll_state(phy); > + phy->state_saved = true; > } > } > > @@ -868,12 +868,12 @@ int msm_dsi_phy_pll_restore_state(struct > msm_dsi_phy *phy) > { > int ret; > > - if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) { > - ret = phy->cfg->pll_ops.restore_state(phy->pll); > + if (phy->cfg->ops.restore_pll_state && phy->state_saved) { > + ret = phy->cfg->ops.restore_pll_state(phy); > if (ret) > return ret; > > - phy->pll->state_saved = false; > + phy->state_saved = false; > } > > return 0; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index b477d21804c8..0b51828c3146 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -17,7 +17,6 @@ > struct msm_dsi_pll { > struct clk_hw clk_hw; > bool pll_on; > - bool state_saved; > > const struct msm_dsi_phy_cfg *cfg; > }; > @@ -29,17 +28,13 @@ struct msm_dsi_phy_ops { > int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, > struct msm_dsi_phy_clk_request *clk_req); > void (*disable)(struct msm_dsi_phy *phy); > -}; > - > -struct msm_dsi_pll_ops { > - void (*save_state)(struct msm_dsi_pll *pll); > - int (*restore_state)(struct msm_dsi_pll *pll); > + void (*save_pll_state)(struct msm_dsi_phy *phy); > + int (*restore_pll_state)(struct msm_dsi_phy *phy); > }; > > struct msm_dsi_phy_cfg { > struct dsi_reg_config reg_cfg; > struct msm_dsi_phy_ops ops; > - const struct msm_dsi_pll_ops pll_ops; > > unsigned long min_pll_rate; > unsigned long max_pll_rate; > @@ -115,6 +110,8 @@ struct msm_dsi_phy { > struct msm_dsi_pll *pll; > > struct clk_hw_onecell_data *provided_clocks; > + > + bool state_saved; > }; > > /* > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index 91ae0f8dbd88..fefff08f83fd 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -518,9 +518,9 @@ static const struct clk_ops > clk_ops_dsi_pll_10nm_vco = { > * PLL Callbacks > */ > > -static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) > +static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); > + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); > struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; > void __iomem *phy_base = pll_10nm->phy_cmn_mmio; > u32 cmn_clk_cfg0, cmn_clk_cfg1; > @@ -541,9 +541,9 @@ static void dsi_pll_10nm_save_state(struct > msm_dsi_pll *pll) > cached->pix_clk_div, cached->pll_mux); > } > > -static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) > +static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); > + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); > struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; > void __iomem *phy_base = pll_10nm->phy_cmn_mmio; > u32 val; > @@ -562,7 +562,9 @@ static int dsi_pll_10nm_restore_state(struct > msm_dsi_pll *pll) > val |= cached->pll_mux; > pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); > > - ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, > pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); > + ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw, > + pll_10nm->vco_current_rate, > + pll_10nm->vco_ref_clk_rate); > if (ret) { > DRM_DEV_ERROR(&pll_10nm->pdev->dev, > "restore vco rate failed. ret=%d\n", ret); > @@ -1005,10 +1007,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = > { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > .pll_init = dsi_pll_10nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_10nm_save_state, > - .restore_state = dsi_pll_10nm_restore_state, > + .save_pll_state = dsi_10nm_pll_save_state, > + .restore_pll_state = dsi_10nm_pll_restore_state, > }, > .min_pll_rate = 1000000000UL, > .max_pll_rate = 3500000000UL, > @@ -1029,10 +1029,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_10nm_8998_cfgs = { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > .pll_init = dsi_pll_10nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_10nm_save_state, > - .restore_state = dsi_pll_10nm_restore_state, > + .save_pll_state = dsi_10nm_pll_save_state, > + .restore_pll_state = dsi_10nm_pll_restore_state, > }, > .min_pll_rate = 1000000000UL, > .max_pll_rate = 3500000000UL, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 91c5bb2fd169..fb22c4b1b765 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -795,9 +795,9 @@ static const struct clk_ops > clk_ops_dsi_pll_14nm_postdiv = { > * PLL Callbacks > */ > > -static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) > +static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); > + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); > struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; > void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; > u32 data; > @@ -810,18 +810,18 @@ static void dsi_pll_14nm_save_state(struct > msm_dsi_pll *pll) > DBG("DSI%d PLL save state %x %x", pll_14nm->id, > cached_state->n1postdiv, cached_state->n2postdiv); > > - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); > + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); > } > > -static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) > +static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); > + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); > struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; > void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; > u32 data; > int ret; > > - ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, > + ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw, > cached_state->vco_rate, 0); > if (ret) { > DRM_DEV_ERROR(&pll_14nm->pdev->dev, > @@ -1166,10 +1166,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = > { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > .pll_init = dsi_pll_14nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_14nm_save_state, > - .restore_state = dsi_pll_14nm_restore_state, > + .save_pll_state = dsi_14nm_pll_save_state, > + .restore_pll_state = dsi_14nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > @@ -1190,10 +1188,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_14nm_660_cfgs = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > .pll_init = dsi_pll_14nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_14nm_save_state, > - .restore_state = dsi_pll_14nm_restore_state, > + .save_pll_state = dsi_14nm_pll_save_state, > + .restore_pll_state = dsi_14nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index 20b31398b540..e589ec8f4cc8 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -470,9 +470,9 @@ static const struct clk_ops > clk_ops_dsi_pll_28nm_vco_lp = { > * PLL Callbacks > */ > > -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) > +static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); > struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; > void __iomem *base = pll_28nm->mmio; > > @@ -481,20 +481,20 @@ static void dsi_pll_28nm_save_state(struct > msm_dsi_pll *pll) > cached_state->postdiv1 = > pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); > cached_state->byte_mux = pll_read(base + > REG_DSI_28nm_PHY_PLL_VREG_CFG); > - if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw)) > - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); > + if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw)) > + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); > else > cached_state->vco_rate = 0; > } > > -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) > +static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); > struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; > void __iomem *base = pll_28nm->mmio; > int ret; > > - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, > + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, > cached_state->vco_rate, 0); > if (ret) { > DRM_DEV_ERROR(&pll_28nm->pdev->dev, > @@ -527,7 +527,7 @@ static int pll_28nm_register(struct dsi_pll_28nm > *pll_28nm, struct clk_hw **prov > > DBG("%d", pll_28nm->id); > > - if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP) > + if (pll_28nm->base.cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; > else > vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; > @@ -783,10 +783,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs > = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > .pll_init = dsi_pll_28nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_28nm_save_state, > - .restore_state = dsi_pll_28nm_restore_state, > + .save_pll_state = dsi_28nm_pll_save_state, > + .restore_pll_state = dsi_28nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > @@ -807,10 +805,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_hpm_famb_cfgs = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > .pll_init = dsi_pll_28nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_28nm_save_state, > - .restore_state = dsi_pll_28nm_restore_state, > + .save_pll_state = dsi_28nm_pll_save_state, > + .restore_pll_state = dsi_28nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > @@ -831,10 +827,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs > = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > .pll_init = dsi_pll_28nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_28nm_save_state, > - .restore_state = dsi_pll_28nm_restore_state, > + .save_pll_state = dsi_28nm_pll_save_state, > + .restore_pll_state = dsi_28nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > index 952444e3e8f0..1e35971b7132 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > @@ -334,9 +334,9 @@ static const struct clk_ops clk_bytediv_ops = { > /* > * PLL Callbacks > */ > -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) > +static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); > struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; > void __iomem *base = pll_28nm->mmio; > > @@ -347,17 +347,17 @@ static void dsi_pll_28nm_save_state(struct > msm_dsi_pll *pll) > cached_state->postdiv1 = > pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); > > - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); > + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); > } > > -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) > +static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); > + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); > struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; > void __iomem *base = pll_28nm->mmio; > int ret; > > - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, > + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, > cached_state->vco_rate, 0); > if (ret) { > DRM_DEV_ERROR(&pll_28nm->pdev->dev, > @@ -662,10 +662,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_8960_cfgs = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > .pll_init = dsi_pll_28nm_8960_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_28nm_save_state, > - .restore_state = dsi_pll_28nm_restore_state, > + .save_pll_state = dsi_28nm_pll_save_state, > + .restore_pll_state = dsi_28nm_pll_restore_state, > }, > .min_pll_rate = VCO_MIN_RATE, > .max_pll_rate = VCO_MAX_RATE, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 321d23b3ed18..8ac57f907ed3 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -543,9 +543,9 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco > = { > * PLL Callbacks > */ > > -static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) > +static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); > + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); > struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; > void __iomem *phy_base = pll_7nm->phy_cmn_mmio; > u32 cmn_clk_cfg0, cmn_clk_cfg1; > @@ -566,9 +566,9 @@ static void dsi_pll_7nm_save_state(struct > msm_dsi_pll *pll) > cached->pix_clk_div, cached->pll_mux); > } > > -static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) > +static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) > { > - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); > + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); > struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; > void __iomem *phy_base = pll_7nm->phy_cmn_mmio; > u32 val; > @@ -587,7 +587,9 @@ static int dsi_pll_7nm_restore_state(struct > msm_dsi_pll *pll) > val |= cached->pll_mux; > pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); > > - ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, > pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); > + ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw, > + pll_7nm->vco_current_rate, > + pll_7nm->vco_ref_clk_rate); > if (ret) { > DRM_DEV_ERROR(&pll_7nm->pdev->dev, > "restore vco rate failed. ret=%d\n", ret); > @@ -1038,10 +1040,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = > { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > .pll_init = dsi_pll_7nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_7nm_save_state, > - .restore_state = dsi_pll_7nm_restore_state, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > }, > .min_pll_rate = 600000000UL, > .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : > ULONG_MAX, > @@ -1063,10 +1063,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_7nm_8150_cfgs = { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > .pll_init = dsi_pll_7nm_init, > - }, > - .pll_ops = { > - .save_state = dsi_pll_7nm_save_state, > - .restore_state = dsi_pll_7nm_restore_state, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > }, > .min_pll_rate = 1000000000UL, > .max_pll_rate = 3500000000UL,
Hi, On Fri, 11 Jun 2021 at 10:07, John Stultz <john.stultz@linaro.org> wrote: > > On Wed, Mar 31, 2021 at 3:58 AM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > > The 7nm, 10nm and 14nm drivers would store interim data used during > > VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data > > structures to the onstack storage. While we are at it, drop > > unused/static 'config' data, unused config fields, etc. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > > Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor > > Hey Dmitry, > Just wanted to give you a heads up. Peter Collingbourne reported > today that his db845c wasn't booting to display for him on his 4k > monitor. It works fine on a 1080p screen, and while 4k isn't supported > (yet?), normally the board should fall back to 1080p when connected > to a 4k monitor. I was able to reproduce this myself and I see the > errors below[1]. It looks like I made a mistake testing these patches with the splash screen disabled. Stephen Boyd has proposed a fix few days ago (will be included into the 5.13). Could you check that it fixes the problem for you? https://lore.kernel.org/linux-arm-msm/20210608195519.125561-1-swboyd@chromium.org/ > > I dug back and found that things were working ok on v5.12 w/ the > recently merged commit d1a97648ae028 ("drm/bridge: lt9611: Fix > handling of 4k panels"), and started digging around. > > Seeing a bunch of changes to the > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c file, I tried reverting a > chunk of the changes since 5.12 to that, and that got it working > again. I've narrowed it down to this change - > 001d8dc33875 ("drm/msm/dsi: remove temp data from global pll > structure") upstream (also reverting following 6e2ad9c3bfca and > 36c5dde5fdf0 first - but its reverting this change that actually makes > it work again). > > I've not managed to really look into the change to see what might be > going wrong yet (its late and I'm about to crash), but I wanted to > give you a heads up. If you have any ideas for me to try I'm happy to > give them a go. > > thanks > -john > > [1]: > [ 19.846857] msm_dsi_phy ae94400.dsi-phy: > [drm:dsi_pll_10nm_vco_prepare] *ERROR* DSI PLL(0) lock failed, > status=0x00000000 > [ 19.857925] msm_dsi_phy ae94400.dsi-phy: > [drm:dsi_pll_10nm_vco_prepare] *ERROR* PLL(0) lock failed > [ 19.866978] dsi_link_clk_enable_6g: Failed to enable dsi byte clk > [ 19.873124] msm_dsi_host_power_on: failed to enable link clocks. ret=-110 > [ 19.879987] dsi_mgr_bridge_pre_enable: power on host 0 failed, -110 > [ 19.886309] Turning OFF PHY while PLL is on > [ 20.415019] lt9611 10-003b: video check: hactive_a=0, hactive_b=0, > vactive=0, v_total=0, h_total_sysclk=0 > [ 20.481062] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > [ 20.489306] [drm:dpu_kms_wait_for_commit_done:453] [dpu error]wait > for commit done returned -110 > [ 20.513031] [drm:dpu_encoder_frame_done_timeout:2161] [dpu > error]enc31 frame done timeout > [ 20.553059] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > [ 20.561300] [drm:dpu_kms_wait_for_commit_done:453] [dpu error]wait > for commit done returned -110 > [ 20.625054] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > [ 20.633299] [drm:dpu_kms_wait_for_commit_done:453] [dpu error]wait > for commit done returned -110 > [ 20.657033] [drm:dpu_encoder_frame_done_timeout:2161] [dpu > error]enc31 frame done timeout > [ 20.697065] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > [ 20.705316] [drm:dpu_kms_wait_for_commit_done:453] [dpu error]wait > for commit done returned -110 > [ 20.769066] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > [ 20.777330] [drm:dpu_kms_wait_for_commit_done:453] [dpu error]wait > for commit done returned -110 > [ 20.801035] [drm:dpu_encoder_frame_done_timeout:2161] [dpu > error]enc31 frame done timeout > [ 20.845049] [drm:dpu_encoder_phys_vid_wait_for_commit_done:528] > [dpu error]vblank timeout > ...