| Message ID | 20210324151846.2774204-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | drm/msm/dsi: refactor MSM DSI PHY/PLL drivers | expand |
Hi Dmitry On 2021-03-24 08:18, Dmitry Baryshkov wrote: > From: Daniel Palmer <daniel@0x0f.com> > > Add a devm helper for clk_hw_register_fixed_factor() so that drivers > that internally > register fixed factor clocks for things like dividers don't need to > manually unregister > them on remove or if probe fails. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > Link: > https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com > Signed-off-by: Stephen Boyd <sboyd@kernel.org> Doesnt this need your signed-off too? Other than that, Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------ > include/linux/clk-provider.h | 4 +++- > 2 files changed, 36 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/clk-fixed-factor.c > b/drivers/clk/clk-fixed-factor.c > index 910e6e74ae90..4f7bf3929d6d 100644 > --- a/drivers/clk/clk-fixed-factor.c > +++ b/drivers/clk/clk-fixed-factor.c > @@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = { > }; > EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); > > +static void devm_clk_hw_register_fixed_factor_release(struct device > *dev, void *res) > +{ > + clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor > *)res)->hw); > +} > + > static struct clk_hw * > __clk_hw_register_fixed_factor(struct device *dev, struct device_node > *np, > const char *name, const char *parent_name, int index, > - unsigned long flags, unsigned int mult, unsigned int div) > + unsigned long flags, unsigned int mult, unsigned int div, > + bool devm) > { > struct clk_fixed_factor *fix; > struct clk_init_data init = { }; > @@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, > struct device_node *np, > struct clk_hw *hw; > int ret; > > - fix = kmalloc(sizeof(*fix), GFP_KERNEL); > + /* You can't use devm without a dev */ > + if (devm && !dev) > + return ERR_PTR(-EINVAL); > + > + if (devm) > + fix = devres_alloc(devm_clk_hw_register_fixed_factor_release, > + sizeof(*fix), GFP_KERNEL); > + else > + fix = kmalloc(sizeof(*fix), GFP_KERNEL); > if (!fix) > return ERR_PTR(-ENOMEM); > > @@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, > struct device_node *np, > else > ret = of_clk_hw_register(np, hw); > if (ret) { > - kfree(fix); > + if (devm) > + devres_free(fix); > + else > + kfree(fix); > hw = ERR_PTR(ret); > - } > + } else if (devm) > + devres_add(dev, fix); > > return hw; > } > @@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct > device *dev, > unsigned int mult, unsigned int div) > { > return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, > -1, > - flags, mult, div); > + flags, mult, div, false); > } > EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); > > @@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw > *hw) > } > EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); > > +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, > + const char *name, const char *parent_name, unsigned long flags, > + unsigned int mult, unsigned int div) > +{ > + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, > -1, > + flags, mult, div, true); > +} > +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); > + > #ifdef CONFIG_OF > static const struct of_device_id set_rate_parent_matches[] = { > { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" }, > @@ -185,7 +212,7 @@ static struct clk_hw > *_of_fixed_factor_clk_setup(struct device_node *node) > flags |= CLK_SET_RATE_PARENT; > > hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0, > - flags, mult, div); > + flags, mult, div, false); > if (IS_ERR(hw)) { > /* > * Clear OF_POPULATED flag so that clock registration can be > diff --git a/include/linux/clk-provider.h > b/include/linux/clk-provider.h > index e4316890661a..58f6fe866ae9 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct > device *dev, > const char *name, const char *parent_name, unsigned long flags, > unsigned int mult, unsigned int div); > void clk_hw_unregister_fixed_factor(struct clk_hw *hw); > - > +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, > + const char *name, const char *parent_name, unsigned long flags, > + unsigned int mult, unsigned int div); > /** > * struct clk_fractional_divider - adjustable fractional divider clock > *
On 2021-03-24 08:18, Dmitry Baryshkov wrote: > Add devm_clk_hw_register_mux() - devres-managed version of > clk_hw_register_mux(). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/clk/clk-mux.c | 35 +++++++++++++++++++++++++++++++++++ > include/linux/clk-provider.h | 13 +++++++++++++ > 2 files changed, 48 insertions(+) > > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c > index e54e79714818..20582aae7a35 100644 > --- a/drivers/clk/clk-mux.c > +++ b/drivers/clk/clk-mux.c > @@ -8,6 +8,7 @@ > */ > > #include <linux/clk-provider.h> > +#include <linux/device.h> > #include <linux/module.h> > #include <linux/slab.h> > #include <linux/io.h> > @@ -206,6 +207,40 @@ struct clk_hw *__clk_hw_register_mux(struct > device *dev, struct device_node *np, > } > EXPORT_SYMBOL_GPL(__clk_hw_register_mux); > > +static void devm_clk_hw_release_mux(struct device *dev, void *res) > +{ > + clk_hw_unregister_mux(*(struct clk_hw **)res); > +} > + > +struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct > device_node *np, > + const char *name, u8 num_parents, > + const char * const *parent_names, > + const struct clk_hw **parent_hws, > + const struct clk_parent_data *parent_data, > + unsigned long flags, void __iomem *reg, u8 shift, u32 mask, > + u8 clk_mux_flags, u32 *table, spinlock_t *lock) > +{ > + struct clk_hw **ptr, *hw; > + > + ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), > GFP_KERNEL); > + if (!ptr) > + return ERR_PTR(-ENOMEM); > + > + hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, > parent_hws, > + parent_data, flags, reg, shift, mask, > + clk_mux_flags, table, lock); > + > + if (!IS_ERR(hw)) { > + *ptr = hw; > + devres_add(dev, ptr); > + } else { > + devres_free(ptr); > + } > + > + return hw; > +} > +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux); > + > struct clk *clk_register_mux_table(struct device *dev, const char > *name, > const char * const *parent_names, u8 num_parents, > unsigned long flags, void __iomem *reg, u8 shift, u32 mask, > diff --git a/include/linux/clk-provider.h > b/include/linux/clk-provider.h > index 58f6fe866ae9..3eb15e0262f5 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -868,6 +868,13 @@ struct clk_hw *__clk_hw_register_mux(struct > device *dev, struct device_node *np, > const struct clk_parent_data *parent_data, > unsigned long flags, void __iomem *reg, u8 shift, u32 mask, > u8 clk_mux_flags, u32 *table, spinlock_t *lock); > +struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct > device_node *np, > + const char *name, u8 num_parents, > + const char * const *parent_names, > + const struct clk_hw **parent_hws, > + const struct clk_parent_data *parent_data, > + unsigned long flags, void __iomem *reg, u8 shift, u32 mask, > + u8 clk_mux_flags, u32 *table, spinlock_t *lock); > struct clk *clk_register_mux_table(struct device *dev, const char > *name, > const char * const *parent_names, u8 num_parents, > unsigned long flags, void __iomem *reg, u8 shift, u32 mask, > @@ -902,6 +909,12 @@ struct clk *clk_register_mux_table(struct device > *dev, const char *name, > __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, > \ > (parent_data), (flags), (reg), (shift), \ > BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) > +#define devm_clk_hw_register_mux(dev, name, parent_names, > num_parents, flags, reg, \ > + shift, width, clk_mux_flags, lock) \ > + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), > \ > + (parent_names), NULL, NULL, (flags), (reg), \ > + (shift), BIT((width)) - 1, (clk_mux_flags), \ > + NULL, (lock)) > > int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int > flags, > unsigned int val);
On 2021-03-24 08:18, Dmitry Baryshkov wrote: > DSI PHY init callback would either map dsi_phy_regulator or > dsi_phy_lane > depending on the PHY type. Replace those callbacks with configuration > options governing mapping those regions. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> This is a nice cleanup which will make all the ioremaps happen in the same location. Hence, Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 42 ++++++++----------- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 19 +-------- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 19 +-------- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 2 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 +-- > .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 19 +-------- > 8 files changed, 31 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index e8c1a727179c..83eb0a630443 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -637,24 +637,6 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy) > return -EINVAL; > } > > -int msm_dsi_phy_init_common(struct msm_dsi_phy *phy) > -{ > - struct platform_device *pdev = phy->pdev; > - int ret = 0; > - > - phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", > - "DSI_PHY_REG"); > - if (IS_ERR(phy->reg_base)) { > - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", > - __func__); > - ret = -ENOMEM; > - goto fail; > - } > - > -fail: > - return ret; > -} > - > static int dsi_phy_driver_probe(struct platform_device *pdev) > { > struct msm_dsi_phy *phy; > @@ -691,6 +673,24 @@ static int dsi_phy_driver_probe(struct > platform_device *pdev) > goto fail; > } > > + if (phy->cfg->has_phy_lane) { > + phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE"); > + if (IS_ERR(phy->lane_base)) { > + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", > __func__); > + ret = -ENOMEM; > + goto fail; > + } > + } > + > + if (phy->cfg->has_phy_regulator) { > + phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", > "DSI_PHY_REG"); > + if (IS_ERR(phy->reg_base)) { > + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator > base\n", __func__); > + ret = -ENOMEM; > + goto fail; > + } > + } > + > ret = dsi_phy_regulator_init(phy); > if (ret) > goto fail; > @@ -702,12 +702,6 @@ static int dsi_phy_driver_probe(struct > platform_device *pdev) > goto fail; > } > > - if (phy->cfg->ops.init) { > - ret = phy->cfg->ops.init(phy); > - if (ret) > - goto fail; > - } > - > /* PLL init will call into clk_register which requires > * register access, so we need to enable power and ahb clock. > */ > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index d2bd74b6f357..03dfb08e7128 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -17,7 +17,6 @@ > #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) > > struct msm_dsi_phy_ops { > - int (*init) (struct msm_dsi_phy *phy); > int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, > struct msm_dsi_phy_clk_request *clk_req); > void (*disable)(struct msm_dsi_phy *phy); > @@ -37,6 +36,8 @@ struct msm_dsi_phy_cfg { > const resource_size_t io_start[DSI_MAX]; > const int num_dsi_phy; > const int quirks; > + bool has_phy_regulator; > + bool has_phy_lane; > }; > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; > @@ -106,7 +107,6 @@ int msm_dsi_dphy_timing_calc_v4(struct > msm_dsi_dphy_timing *timing, > struct msm_dsi_phy_clk_request *clk_req); > void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 > reg, > u32 bit_mask); > -int msm_dsi_phy_init_common(struct msm_dsi_phy *phy); > > #endif /* __DSI_PHY_H__ */ > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index d1b92d4dc197..655fa17a0452 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -216,24 +216,10 @@ static void dsi_10nm_phy_disable(struct > msm_dsi_phy *phy) > DBG("DSI%d PHY disabled", phy->id); > } > > -static int dsi_10nm_phy_init(struct msm_dsi_phy *phy) > -{ > - struct platform_device *pdev = phy->pdev; > - > - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", > - "DSI_PHY_LANE"); > - if (IS_ERR(phy->lane_base)) { > - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", > - __func__); > - return -ENOMEM; > - } > - > - return 0; > -} > - > const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { > .type = MSM_DSI_PHY_10NM, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -243,7 +229,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { > .ops = { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > - .init = dsi_10nm_phy_init, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > @@ -252,6 +237,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { > const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { > .type = MSM_DSI_PHY_10NM, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -261,7 +247,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs > = { > .ops = { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > - .init = dsi_10nm_phy_init, > }, > .io_start = { 0xc994400, 0xc996400 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 519400501bcd..6989730b5fbd 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -129,24 +129,10 @@ static void dsi_14nm_phy_disable(struct > msm_dsi_phy *phy) > wmb(); > } > > -static int dsi_14nm_phy_init(struct msm_dsi_phy *phy) > -{ > - struct platform_device *pdev = phy->pdev; > - > - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", > - "DSI_PHY_LANE"); > - if (IS_ERR(phy->lane_base)) { > - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", > - __func__); > - return -ENOMEM; > - } > - > - return 0; > -} > - > const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { > .type = MSM_DSI_PHY_14NM, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -156,7 +142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { > .ops = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > - .init = dsi_14nm_phy_init, > }, > .io_start = { 0x994400, 0x996400 }, > .num_dsi_phy = 2, > @@ -165,6 +150,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { > const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { > .type = MSM_DSI_PHY_14NM, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -174,7 +160,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs > = { > .ops = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > - .init = dsi_14nm_phy_init, > }, > .io_start = { 0xc994400, 0xc996000 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c > index eca86bf448f7..b752636f7f21 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c > @@ -127,6 +127,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy > *phy) > const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { > .type = MSM_DSI_PHY_20NM, > .src_pll_truthtable = { {false, true}, {false, true} }, > + .has_phy_regulator = true, > .reg_cfg = { > .num = 2, > .regs = { > @@ -137,7 +138,6 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { > .ops = { > .enable = dsi_20nm_phy_enable, > .disable = dsi_20nm_phy_disable, > - .init = msm_dsi_phy_init_common, > }, > .io_start = { 0xfd998500, 0xfd9a0500 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index c3c580cfd8b1..5bf79de0da67 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -153,6 +153,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy > *phy) > const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { > .type = MSM_DSI_PHY_28NM_HPM, > .src_pll_truthtable = { {true, true}, {false, true} }, > + .has_phy_regulator = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -162,7 +163,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs > = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > - .init = msm_dsi_phy_init_common, > }, > .io_start = { 0xfd922b00, 0xfd923100 }, > .num_dsi_phy = 2, > @@ -171,6 +171,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs > = { > const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { > .type = MSM_DSI_PHY_28NM_HPM, > .src_pll_truthtable = { {true, true}, {false, true} }, > + .has_phy_regulator = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -180,7 +181,6 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_hpm_famb_cfgs = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > - .init = msm_dsi_phy_init_common, > }, > .io_start = { 0x1a94400, 0x1a96400 }, > .num_dsi_phy = 2, > @@ -189,6 +189,7 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_hpm_famb_cfgs = { > const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { > .type = MSM_DSI_PHY_28NM_LP, > .src_pll_truthtable = { {true, true}, {true, true} }, > + .has_phy_regulator = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -198,7 +199,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = > { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > - .init = msm_dsi_phy_init_common, > }, > .io_start = { 0x1a98500 }, > .num_dsi_phy = 1, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > index f22583353957..5d33de27a0f4 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > @@ -176,6 +176,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy > *phy) > const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { > .type = MSM_DSI_PHY_28NM_8960, > .src_pll_truthtable = { {true, true}, {false, true} }, > + .has_phy_regulator = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -185,7 +186,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs > = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > - .init = msm_dsi_phy_init_common, > }, > .io_start = { 0x4700300, 0x5800300 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 79c034ae075d..cbfeec860e69 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -224,24 +224,10 @@ static void dsi_7nm_phy_disable(struct > msm_dsi_phy *phy) > DBG("DSI%d PHY disabled", phy->id); > } > > -static int dsi_7nm_phy_init(struct msm_dsi_phy *phy) > -{ > - struct platform_device *pdev = phy->pdev; > - > - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", > - "DSI_PHY_LANE"); > - if (IS_ERR(phy->lane_base)) { > - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", > - __func__); > - return -ENOMEM; > - } > - > - return 0; > -} > - > const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > .type = MSM_DSI_PHY_7NM_V4_1, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -251,7 +237,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > .ops = { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > - .init = dsi_7nm_phy_init, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > @@ -260,6 +245,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { > .type = MSM_DSI_PHY_7NM, > .src_pll_truthtable = { {false, false}, {true, false} }, > + .has_phy_lane = true, > .reg_cfg = { > .num = 1, > .regs = { > @@ -269,7 +255,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs > = { > .ops = { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > - .init = dsi_7nm_phy_init, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2,
On 2021-03-24 08:18, Dmitry Baryshkov wrote: > Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits > the amount of data in the struct msm_dsi_pll. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/dsi.h | 6 -- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 14 ++-- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 15 +++++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 38 ++++++++--- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 47 ++++++++----- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 65 ++++++++++++------ > .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 33 +++++---- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 49 +++++++++----- > drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 67 ++++--------------- > drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 67 +------------------ > 10 files changed, 191 insertions(+), 210 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi.h > b/drivers/gpu/drm/msm/dsi/dsi.h > index 78ef5d4ed922..21cf883fb6f1 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi.h > +++ b/drivers/gpu/drm/msm/dsi/dsi.h > @@ -107,8 +107,6 @@ struct drm_encoder *msm_dsi_get_encoder(struct > msm_dsi *msm_dsi); > /* dsi pll */ > struct msm_dsi_pll; > #ifdef CONFIG_DRM_MSM_DSI_PLL > -struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, > - enum msm_dsi_phy_type type, int dsi_id); > void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); > int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, > struct clk **byte_clk_provider, struct clk **pixel_clk_provider); > @@ -117,10 +115,6 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll > *pll); > int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, > enum msm_dsi_phy_usecase uc); > #else > -static inline struct msm_dsi_pll *msm_dsi_pll_init(struct > platform_device *pdev, > - enum msm_dsi_phy_type type, int id) { > - return ERR_PTR(-ENODEV); > -} > static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) > { > } > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 83eb0a630443..5f153b683521 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -709,12 +709,14 @@ static int dsi_phy_driver_probe(struct > platform_device *pdev) > if (ret) > goto fail; > > - phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); > - if (IS_ERR_OR_NULL(phy->pll)) { > - DRM_DEV_INFO(dev, > - "%s: pll init failed: %ld, need separate pll clk driver\n", > - __func__, PTR_ERR(phy->pll)); > - phy->pll = NULL; > + if (phy->cfg->ops.pll_init) { > + ret = phy->cfg->ops.pll_init(phy); > + if (ret) { > + DRM_DEV_INFO(dev, > + "%s: pll init failed: %d, need separate pll clk driver\n", > + __func__, ret); > + goto fail; > + } > } > > dsi_phy_disable_resource(phy); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 03dfb08e7128..244d2c900d40 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -17,15 +17,30 @@ > #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) > > struct msm_dsi_phy_ops { > + int (*pll_init)(struct msm_dsi_phy *phy); > int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, > struct msm_dsi_phy_clk_request *clk_req); > void (*disable)(struct msm_dsi_phy *phy); > }; > > +struct msm_dsi_pll_ops { > + int (*enable_seq)(struct msm_dsi_pll *pll); > + void (*disable_seq)(struct msm_dsi_pll *pll); > + int (*get_provider)(struct msm_dsi_pll *pll, > + struct clk **byte_clk_provider, > + struct clk **pixel_clk_provider); > + void (*destroy)(struct msm_dsi_pll *pll); > + void (*save_state)(struct msm_dsi_pll *pll); > + int (*restore_state)(struct msm_dsi_pll *pll); > + int (*set_usecase)(struct msm_dsi_pll *pll, > + enum msm_dsi_phy_usecase uc); > +}; > + > struct msm_dsi_phy_cfg { > enum msm_dsi_phy_type type; > struct dsi_reg_config reg_cfg; > struct msm_dsi_phy_ops ops; > + const struct msm_dsi_pll_ops pll_ops; > > /* > * Each cell {phy_id, pll_id} of the truth table indicates > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index 5da369b5c475..f697ff9a0d8e 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -828,15 +828,17 @@ static int pll_10nm_register(struct dsi_pll_10nm > *pll_10nm) > return ret; > } > > -struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device > *pdev, int id) > +static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) > { > + struct platform_device *pdev = phy->pdev; > + int id = phy->id; > struct dsi_pll_10nm *pll_10nm; > struct msm_dsi_pll *pll; > int ret; > > pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); > if (!pll_10nm) > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > > DBG("DSI PLL%d", id); > > @@ -847,13 +849,13 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct > platform_device *pdev, int id) > pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); > if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); > if (IS_ERR_OR_NULL(pll_10nm->mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > spin_lock_init(&pll_10nm->postdiv_lock); > @@ -861,24 +863,22 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct > platform_device *pdev, int id) > pll = &pll_10nm->base; > pll->min_rate = 1000000000UL; > pll->max_rate = 3500000000UL; > - pll->get_provider = dsi_pll_10nm_get_provider; > - pll->destroy = dsi_pll_10nm_destroy; > - pll->save_state = dsi_pll_10nm_save_state; > - pll->restore_state = dsi_pll_10nm_restore_state; > - pll->set_usecase = dsi_pll_10nm_set_usecase; > + pll->cfg = phy->cfg; > > pll_10nm->vco_delay = 1; > > ret = pll_10nm_register(pll_10nm); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > - return ERR_PTR(ret); > + return ret; > } > > + phy->pll = pll; > + > /* TODO: Remove this when we have proper display handover support */ > msm_dsi_pll_save_state(pll); > > - return pll; > + return 0; > } > > static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy) > @@ -1102,6 +1102,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = > { > .ops = { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > + .pll_init = dsi_pll_10nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_10nm_get_provider, > + .destroy = dsi_pll_10nm_destroy, > + .save_state = dsi_pll_10nm_save_state, > + .restore_state = dsi_pll_10nm_restore_state, > + .set_usecase = dsi_pll_10nm_set_usecase, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > @@ -1120,6 +1128,14 @@ const struct msm_dsi_phy_cfg > dsi_phy_10nm_8998_cfgs = { > .ops = { > .enable = dsi_10nm_phy_enable, > .disable = dsi_10nm_phy_disable, > + .pll_init = dsi_pll_10nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_10nm_get_provider, > + .destroy = dsi_pll_10nm_destroy, > + .save_state = dsi_pll_10nm_save_state, > + .restore_state = dsi_pll_10nm_restore_state, > + .set_usecase = dsi_pll_10nm_set_usecase, > }, > .io_start = { 0xc994400, 0xc996400 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 4386edfa91fe..011d285bf2c0 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -1042,18 +1042,20 @@ static int pll_14nm_register(struct > dsi_pll_14nm *pll_14nm) > return 0; > } > > -struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device > *pdev, int id) > +static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) > { > + struct platform_device *pdev = phy->pdev; > + int id = phy->id; > struct dsi_pll_14nm *pll_14nm; > struct msm_dsi_pll *pll; > int ret; > > if (!pdev) > - return ERR_PTR(-ENODEV); > + return -ENODEV; > > pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); > if (!pll_14nm) > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > > DBG("PLL%d", id); > > @@ -1064,13 +1066,13 @@ struct msm_dsi_pll > *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) > pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); > if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); > if (IS_ERR_OR_NULL(pll_14nm->mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > spin_lock_init(&pll_14nm->postdiv_lock); > @@ -1078,24 +1080,19 @@ struct msm_dsi_pll > *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) > pll = &pll_14nm->base; > pll->min_rate = VCO_MIN_RATE; > pll->max_rate = VCO_MAX_RATE; > - pll->get_provider = dsi_pll_14nm_get_provider; > - pll->destroy = dsi_pll_14nm_destroy; > - pll->disable_seq = dsi_pll_14nm_disable_seq; > - pll->save_state = dsi_pll_14nm_save_state; > - pll->restore_state = dsi_pll_14nm_restore_state; > - pll->set_usecase = dsi_pll_14nm_set_usecase; > + pll->cfg = phy->cfg; > > pll_14nm->vco_delay = 1; > > - pll->enable_seq = dsi_pll_14nm_enable_seq; > - > ret = pll_14nm_register(pll_14nm); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > - return ERR_PTR(ret); > + return ret; > } > > - return pll; > + phy->pll = pll; > + > + return 0; > } > > static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, > @@ -1230,6 +1227,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = > { > .ops = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > + .pll_init = dsi_pll_14nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_14nm_get_provider, > + .destroy = dsi_pll_14nm_destroy, > + .save_state = dsi_pll_14nm_save_state, > + .restore_state = dsi_pll_14nm_restore_state, > + .set_usecase = dsi_pll_14nm_set_usecase, > + .disable_seq = dsi_pll_14nm_disable_seq, > + .enable_seq = dsi_pll_14nm_enable_seq, > }, > .io_start = { 0x994400, 0x996400 }, > .num_dsi_phy = 2, > @@ -1248,6 +1255,16 @@ const struct msm_dsi_phy_cfg > dsi_phy_14nm_660_cfgs = { > .ops = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, > + .pll_init = dsi_pll_14nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_14nm_get_provider, > + .destroy = dsi_pll_14nm_destroy, > + .save_state = dsi_pll_14nm_save_state, > + .restore_state = dsi_pll_14nm_restore_state, > + .set_usecase = dsi_pll_14nm_set_usecase, > + .disable_seq = dsi_pll_14nm_disable_seq, > + .enable_seq = dsi_pll_14nm_enable_seq, > }, > .io_start = { 0xc994400, 0xc996000 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index 760cf7956fa2..fb6e19d9495d 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -597,19 +597,20 @@ static int pll_28nm_register(struct dsi_pll_28nm > *pll_28nm) > return 0; > } > > -struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device > *pdev, > - enum msm_dsi_phy_type type, int id) > +static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) > { > + struct platform_device *pdev = phy->pdev; > + int id = phy->id; > struct dsi_pll_28nm *pll_28nm; > struct msm_dsi_pll *pll; > int ret; > > if (!pdev) > - return ERR_PTR(-ENODEV); > + return -ENODEV; > > pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); > if (!pll_28nm) > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > > pll_28nm->pdev = pdev; > pll_28nm->id = id; > @@ -617,40 +618,33 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct > platform_device *pdev, > pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); > if (IS_ERR_OR_NULL(pll_28nm->mmio)) { > DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > pll = &pll_28nm->base; > pll->min_rate = VCO_MIN_RATE; > pll->max_rate = VCO_MAX_RATE; > - pll->get_provider = dsi_pll_28nm_get_provider; > - pll->destroy = dsi_pll_28nm_destroy; > - pll->disable_seq = dsi_pll_28nm_disable_seq; > - pll->save_state = dsi_pll_28nm_save_state; > - pll->restore_state = dsi_pll_28nm_restore_state; > - > - if (type == MSM_DSI_PHY_28NM_HPM) { > + if (phy->cfg->type == MSM_DSI_PHY_28NM_HPM) { > pll_28nm->vco_delay = 1; > - > - pll->enable_seq = dsi_pll_28nm_enable_seq_hpm; > - } else if (type == MSM_DSI_PHY_28NM_LP) { > + } else if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) { > pll_28nm->vco_delay = 1000; > - > - pll->enable_seq = dsi_pll_28nm_enable_seq_lp; > } else { > - DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type); > - return ERR_PTR(-EINVAL); > + DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", > phy->cfg->type); > + return -EINVAL; > } > > + pll->cfg = phy->cfg; > + > ret = pll_28nm_register(pll_28nm); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > - return ERR_PTR(ret); > + return ret; > } > > - return pll; > -} > + phy->pll = pll; > > + return 0; > +} > > static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, > struct msm_dsi_dphy_timing *timing) > @@ -809,6 +803,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs > = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > + .pll_init = dsi_pll_28nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_28nm_get_provider, > + .destroy = dsi_pll_28nm_destroy, > + .save_state = dsi_pll_28nm_save_state, > + .restore_state = dsi_pll_28nm_restore_state, > + .disable_seq = dsi_pll_28nm_disable_seq, > + .enable_seq = dsi_pll_28nm_enable_seq_hpm, > }, > .io_start = { 0xfd922b00, 0xfd923100 }, > .num_dsi_phy = 2, > @@ -827,6 +830,15 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_hpm_famb_cfgs = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > + .pll_init = dsi_pll_28nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_28nm_get_provider, > + .destroy = dsi_pll_28nm_destroy, > + .save_state = dsi_pll_28nm_save_state, > + .restore_state = dsi_pll_28nm_restore_state, > + .disable_seq = dsi_pll_28nm_disable_seq, > + .enable_seq = dsi_pll_28nm_enable_seq_hpm, > }, > .io_start = { 0x1a94400, 0x1a96400 }, > .num_dsi_phy = 2, > @@ -845,6 +857,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs > = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > + .pll_init = dsi_pll_28nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_28nm_get_provider, > + .destroy = dsi_pll_28nm_destroy, > + .save_state = dsi_pll_28nm_save_state, > + .restore_state = dsi_pll_28nm_restore_state, > + .disable_seq = dsi_pll_28nm_disable_seq, > + .enable_seq = dsi_pll_28nm_enable_seq_lp, > }, > .io_start = { 0x1a98500 }, > .num_dsi_phy = 1, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > index 2cfb7edf91d8..08f31be3b0dc 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > @@ -483,19 +483,20 @@ static int pll_28nm_register(struct dsi_pll_28nm > *pll_28nm) > return 0; > } > > -struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device > *pdev, > - int id) > +static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) > { > + struct platform_device *pdev = phy->pdev; > + int id = phy->id; > struct dsi_pll_28nm *pll_28nm; > struct msm_dsi_pll *pll; > int ret; > > if (!pdev) > - return ERR_PTR(-ENODEV); > + return -ENODEV; > > pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); > if (!pll_28nm) > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > > pll_28nm->pdev = pdev; > pll_28nm->id = id + 1; > @@ -503,27 +504,24 @@ struct msm_dsi_pll > *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, > pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); > if (IS_ERR_OR_NULL(pll_28nm->mmio)) { > DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > pll = &pll_28nm->base; > pll->min_rate = VCO_MIN_RATE; > pll->max_rate = VCO_MAX_RATE; > - pll->get_provider = dsi_pll_28nm_get_provider; > - pll->destroy = dsi_pll_28nm_destroy; > - pll->disable_seq = dsi_pll_28nm_disable_seq; > - pll->save_state = dsi_pll_28nm_save_state; > - pll->restore_state = dsi_pll_28nm_restore_state; > > - pll->enable_seq = dsi_pll_28nm_enable_seq; > + pll->cfg = phy->cfg; > > ret = pll_28nm_register(pll_28nm); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > - return ERR_PTR(ret); > + return ret; > } > > - return pll; > + phy->pll = pll; > + > + return 0; > } > > static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, > @@ -704,6 +702,15 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_8960_cfgs = { > .ops = { > .enable = dsi_28nm_phy_enable, > .disable = dsi_28nm_phy_disable, > + .pll_init = dsi_pll_28nm_8960_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_28nm_get_provider, > + .destroy = dsi_pll_28nm_destroy, > + .save_state = dsi_pll_28nm_save_state, > + .restore_state = dsi_pll_28nm_restore_state, > + .disable_seq = dsi_pll_28nm_disable_seq, > + .enable_seq = dsi_pll_28nm_enable_seq, > }, > .io_start = { 0x4700300, 0x5800300 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index f9af9d70b56a..68b54e5060e4 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -178,7 +178,7 @@ static void dsi_pll_calc_dec_frac(struct > dsi_pll_7nm *pll) > > dec = div_u64(dec_multiple, multiplier); > > - if (pll->base.type != MSM_DSI_PHY_7NM_V4_1) > + if (pll->base.cfg->type != MSM_DSI_PHY_7NM_V4_1) > regs->pll_clock_inverters = 0x28; > else if (pll_freq <= 1000000000ULL) > regs->pll_clock_inverters = 0xa0; > @@ -273,7 +273,7 @@ static void dsi_pll_config_hzindep_reg(struct > dsi_pll_7nm *pll) > void __iomem *base = pll->mmio; > u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; > > - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { > + if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { > if (pll->vco_current_rate >= 3100000000ULL) > analog_controls_five_1 = 0x03; > > @@ -307,9 +307,9 @@ static void dsi_pll_config_hzindep_reg(struct > dsi_pll_7nm *pll) > pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); > pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); > pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, > - pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); > + pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); > > - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { > + if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { > pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); > if (pll->slave) > pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, > 0x22); > @@ -853,16 +853,17 @@ static int pll_7nm_register(struct dsi_pll_7nm > *pll_7nm) > return ret; > } > > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > - enum msm_dsi_phy_type type, int id) > +static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) > { > + struct platform_device *pdev = phy->pdev; > + int id = phy->id; > struct dsi_pll_7nm *pll_7nm; > struct msm_dsi_pll *pll; > int ret; > > pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); > if (!pll_7nm) > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > > DBG("DSI PLL%d", id); > > @@ -873,13 +874,13 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct > platform_device *pdev, > pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); > if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); > if (IS_ERR_OR_NULL(pll_7nm->mmio)) { > DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); > - return ERR_PTR(-ENOMEM); > + return -ENOMEM; > } > > spin_lock_init(&pll_7nm->postdiv_lock); > @@ -887,30 +888,28 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct > platform_device *pdev, > pll = &pll_7nm->base; > pll->min_rate = 1000000000UL; > pll->max_rate = 3500000000UL; > - if (type == MSM_DSI_PHY_7NM_V4_1) { > + if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) { > pll->min_rate = 600000000UL; > pll->max_rate = (unsigned long)5000000000ULL; > /* workaround for max rate overflowing on 32-bit builds: */ > pll->max_rate = max(pll->max_rate, 0xffffffffUL); > } > - pll->get_provider = dsi_pll_7nm_get_provider; > - pll->destroy = dsi_pll_7nm_destroy; > - pll->save_state = dsi_pll_7nm_save_state; > - pll->restore_state = dsi_pll_7nm_restore_state; > - pll->set_usecase = dsi_pll_7nm_set_usecase; > + pll->cfg = phy->cfg; > > pll_7nm->vco_delay = 1; > > ret = pll_7nm_register(pll_7nm); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > - return ERR_PTR(ret); > + return ret; > } > > + phy->pll = pll; > + > /* TODO: Remove this when we have proper display handover support */ > msm_dsi_pll_save_state(pll); > > - return pll; > + return 0; > } > > static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) > @@ -1142,6 +1141,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = > { > .ops = { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_7nm_get_provider, > + .destroy = dsi_pll_7nm_destroy, > + .save_state = dsi_pll_7nm_save_state, > + .restore_state = dsi_pll_7nm_restore_state, > + .set_usecase = dsi_pll_7nm_set_usecase, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > @@ -1160,6 +1167,14 @@ const struct msm_dsi_phy_cfg > dsi_phy_7nm_8150_cfgs = { > .ops = { > .enable = dsi_7nm_phy_enable, > .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + }, > + .pll_ops = { > + .get_provider = dsi_pll_7nm_get_provider, > + .destroy = dsi_pll_7nm_destroy, > + .save_state = dsi_pll_7nm_save_state, > + .restore_state = dsi_pll_7nm_restore_state, > + .set_usecase = dsi_pll_7nm_set_usecase, > }, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > index 9e9fa90bf504..c7ff0eba0e8b 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. > */ > > +#include "dsi_phy.h" > #include "dsi_pll.h" > > /* > @@ -33,7 +34,7 @@ int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) > if (unlikely(pll->pll_on)) > return 0; > > - ret = pll->enable_seq(pll); > + ret = pll->cfg->pll_ops.enable_seq(pll); > if (ret) { > DRM_ERROR("DSI PLL failed to lock\n"); > return ret; > @@ -51,7 +52,7 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw > *hw) > if (unlikely(!pll->pll_on)) > return; > > - pll->disable_seq(pll); > + pll->cfg->pll_ops.disable_seq(pll); > > pll->pll_on = false; > } > @@ -76,8 +77,8 @@ void msm_dsi_pll_helper_unregister_clks(struct > platform_device *pdev, > int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, > struct clk **byte_clk_provider, struct clk **pixel_clk_provider) > { > - if (pll->get_provider) > - return pll->get_provider(pll, > + if (pll->cfg->pll_ops.get_provider) > + return pll->cfg->pll_ops.get_provider(pll, > byte_clk_provider, > pixel_clk_provider); > > @@ -86,14 +87,14 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll > *pll, > > void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) > { > - if (pll->destroy) > - pll->destroy(pll); > + if (pll->cfg->pll_ops.destroy) > + pll->cfg->pll_ops.destroy(pll); > } > > void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) > { > - if (pll->save_state) { > - pll->save_state(pll); > + if (pll->cfg->pll_ops.save_state) { > + pll->cfg->pll_ops.save_state(pll); > pll->state_saved = true; > } > } > @@ -102,8 +103,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll > *pll) > { > int ret; > > - if (pll->restore_state && pll->state_saved) { > - ret = pll->restore_state(pll); > + if (pll->cfg->pll_ops.restore_state && pll->state_saved) { > + ret = pll->cfg->pll_ops.restore_state(pll); > if (ret) > return ret; > > @@ -116,50 +117,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll > *pll) > int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, > enum msm_dsi_phy_usecase uc) > { > - if (pll->set_usecase) > - return pll->set_usecase(pll, uc); > + if (pll->cfg->pll_ops.set_usecase) > + return pll->cfg->pll_ops.set_usecase(pll, uc); > > return 0; > } > - > -struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, > - enum msm_dsi_phy_type type, int id) > -{ > - struct device *dev = &pdev->dev; > - struct msm_dsi_pll *pll; > - > - switch (type) { > - case MSM_DSI_PHY_28NM_HPM: > - case MSM_DSI_PHY_28NM_LP: > - pll = msm_dsi_pll_28nm_init(pdev, type, id); > - break; > - case MSM_DSI_PHY_28NM_8960: > - pll = msm_dsi_pll_28nm_8960_init(pdev, id); > - break; > - case MSM_DSI_PHY_14NM: > - pll = msm_dsi_pll_14nm_init(pdev, id); > - break; > - case MSM_DSI_PHY_10NM: > - pll = msm_dsi_pll_10nm_init(pdev, id); > - break; > - case MSM_DSI_PHY_7NM: > - case MSM_DSI_PHY_7NM_V4_1: > - pll = msm_dsi_pll_7nm_init(pdev, type, id); > - break; > - default: > - pll = ERR_PTR(-ENXIO); > - break; > - } > - > - if (IS_ERR(pll)) { > - DRM_DEV_ERROR(dev, "%s: failed to init DSI PLL\n", __func__); > - return pll; > - } > - > - pll->type = type; > - > - DBG("DSI:%d PLL registered", id); > - > - return pll; > -} > - > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > index eebf90671eec..4fa73fbcba52 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > @@ -14,8 +14,6 @@ > #define NUM_DSI_CLOCKS_MAX 6 > > struct msm_dsi_pll { > - enum msm_dsi_phy_type type; > - > struct clk_hw clk_hw; > bool pll_on; > bool state_saved; > @@ -23,16 +21,7 @@ struct msm_dsi_pll { > unsigned long min_rate; > unsigned long max_rate; > > - int (*enable_seq)(struct msm_dsi_pll *pll); > - void (*disable_seq)(struct msm_dsi_pll *pll); > - int (*get_provider)(struct msm_dsi_pll *pll, > - struct clk **byte_clk_provider, > - struct clk **pixel_clk_provider); > - void (*destroy)(struct msm_dsi_pll *pll); > - void (*save_state)(struct msm_dsi_pll *pll); > - int (*restore_state)(struct msm_dsi_pll *pll); > - int (*set_usecase)(struct msm_dsi_pll *pll, > - enum msm_dsi_phy_usecase uc); > + const struct msm_dsi_phy_cfg *cfg; > }; > > #define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) > @@ -72,59 +61,5 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw > *hw); > void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, > struct clk **clks, u32 num_clks); > > -/* > - * Initialization for Each PLL Type > - */ > -#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device > *pdev, > - enum msm_dsi_phy_type type, int id); > -#else > -static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init( > - struct platform_device *pdev, enum msm_dsi_phy_type type, int id) > -{ > - return ERR_PTR(-ENODEV); > -} > -#endif > -#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY > -struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device > *pdev, > - int id); > -#else > -static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init( > - struct platform_device *pdev, int id) > -{ > - return ERR_PTR(-ENODEV); > -} > -#endif > - > -#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device > *pdev, int id); > -#else > -static inline struct msm_dsi_pll * > -msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) > -{ > - return ERR_PTR(-ENODEV); > -} > -#endif > -#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device > *pdev, int id); > -#else > -static inline struct msm_dsi_pll * > -msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) > -{ > - return ERR_PTR(-ENODEV); > -} > -#endif > -#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > - enum msm_dsi_phy_type type, int id); > -#else > -static inline struct msm_dsi_pll * > -msm_dsi_pll_7nm_init(struct platform_device *pdev, > - enum msm_dsi_phy_type type, int id) > -{ > - return ERR_PTR(-ENODEV); > -} > -#endif > - > #endif /* __DSI_PLL_H__ */
On 2021-03-24 08:18, Dmitry Baryshkov wrote: > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 ++++-- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 ++++-- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 8 ++++++-- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 ++-- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 ++++-------- > drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 8 ++++---- > drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 --- > 8 files changed, 27 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 39abb86446f9..000e4207dabc 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg { > struct msm_dsi_phy_ops ops; > const struct msm_dsi_pll_ops pll_ops; > > + unsigned long min_pll_rate; > + unsigned long max_pll_rate; > + > /* > * Each cell {phy_id, pll_id} of the truth table indicates > * if the source PLL selection bit should be set for each PHY. > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index dc8ccc994759..5f9d0cfc4e03 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy > *phy) > spin_lock_init(&pll_10nm->postdiv_lock); > > pll = &pll_10nm->base; > - pll->min_rate = 1000000000UL; > - pll->max_rate = 3500000000UL; > pll->cfg = phy->cfg; > > pll_10nm->vco_delay = 1; > @@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = > { > .restore_state = dsi_pll_10nm_restore_state, > .set_usecase = dsi_pll_10nm_set_usecase, > }, > + .min_pll_rate = 1000000000UL, > + .max_pll_rate = 3500000000UL, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > }; > @@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_10nm_8998_cfgs = { > .restore_state = dsi_pll_10nm_restore_state, > .set_usecase = dsi_pll_10nm_set_usecase, > }, > + .min_pll_rate = 1000000000UL, > + .max_pll_rate = 3500000000UL, > .io_start = { 0xc994400, 0xc996400 }, > .num_dsi_phy = 2, > .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index d78f846cf8e4..8e4528301e5d 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -1078,8 +1078,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy > *phy) > spin_lock_init(&pll_14nm->postdiv_lock); > > pll = &pll_14nm->base; > - pll->min_rate = VCO_MIN_RATE; > - pll->max_rate = VCO_MAX_RATE; > pll->cfg = phy->cfg; > > pll_14nm->vco_delay = 1; > @@ -1237,6 +1235,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = > { > .disable_seq = dsi_pll_14nm_disable_seq, > .enable_seq = dsi_pll_14nm_enable_seq, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0x994400, 0x996400 }, > .num_dsi_phy = 2, > }; > @@ -1264,6 +1264,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_14nm_660_cfgs = { > .disable_seq = dsi_pll_14nm_disable_seq, > .enable_seq = dsi_pll_14nm_enable_seq, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0xc994400, 0xc996000 }, > .num_dsi_phy = 2, > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index bb33261d606d..d267b25e5da0 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -625,8 +625,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy > *phy) > } > > pll = &pll_28nm->base; > - pll->min_rate = VCO_MIN_RATE; > - pll->max_rate = VCO_MAX_RATE; > if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) > pll_28nm->vco_delay = 1000; > else > @@ -811,6 +809,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs > = { > .disable_seq = dsi_pll_28nm_disable_seq, > .enable_seq = dsi_pll_28nm_enable_seq_hpm, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0xfd922b00, 0xfd923100 }, > .num_dsi_phy = 2, > }; > @@ -837,6 +837,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_28nm_hpm_famb_cfgs = { > .disable_seq = dsi_pll_28nm_disable_seq, > .enable_seq = dsi_pll_28nm_enable_seq_hpm, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0x1a94400, 0x1a96400 }, > .num_dsi_phy = 2, > }; > @@ -863,6 +865,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = > { > .disable_seq = dsi_pll_28nm_disable_seq, > .enable_seq = dsi_pll_28nm_enable_seq_lp, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0x1a98500 }, > .num_dsi_phy = 1, > .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > index 79b0842a8dc4..31e7910c6050 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c > @@ -508,8 +508,6 @@ static int dsi_pll_28nm_8960_init(struct > msm_dsi_phy *phy) > } > > pll = &pll_28nm->base; > - pll->min_rate = VCO_MIN_RATE; > - pll->max_rate = VCO_MAX_RATE; > > pll->cfg = phy->cfg; > > @@ -711,6 +709,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs > = { > .disable_seq = dsi_pll_28nm_disable_seq, > .enable_seq = dsi_pll_28nm_enable_seq, > }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > .io_start = { 0x4700300, 0x5800300 }, > .num_dsi_phy = 2, > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 44ae495e8fca..4831d6769da7 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -889,14 +889,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy > *phy) > spin_lock_init(&pll_7nm->postdiv_lock); > > pll = &pll_7nm->base; > - pll->min_rate = 1000000000UL; > - pll->max_rate = 3500000000UL; > - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > - pll->min_rate = 600000000UL; > - pll->max_rate = (unsigned long)5000000000ULL; > - /* workaround for max rate overflowing on 32-bit builds: */ > - pll->max_rate = max(pll->max_rate, 0xffffffffUL); > - } > pll->cfg = phy->cfg; > > pll_7nm->vco_delay = 1; > @@ -1152,6 +1144,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > .restore_state = dsi_pll_7nm_restore_state, > .set_usecase = dsi_pll_7nm_set_usecase, > }, > + .min_pll_rate = 600000000UL, > + .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : > ULONG_MAX, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > .quirks = DSI_PHY_7NM_QUIRK_V4_1, > @@ -1178,6 +1172,8 @@ const struct msm_dsi_phy_cfg > dsi_phy_7nm_8150_cfgs = { > .restore_state = dsi_pll_7nm_restore_state, > .set_usecase = dsi_pll_7nm_set_usecase, > }, > + .min_pll_rate = 1000000000UL, > + .max_pll_rate = 3500000000UL, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > index c7ff0eba0e8b..e607adffe001 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c > @@ -14,10 +14,10 @@ long msm_dsi_pll_helper_clk_round_rate(struct > clk_hw *hw, > { > struct msm_dsi_pll *pll = hw_clk_to_pll(hw); > > - if (rate < pll->min_rate) > - return pll->min_rate; > - else if (rate > pll->max_rate) > - return pll->max_rate; > + if (rate < pll->cfg->min_pll_rate) > + return pll->cfg->min_pll_rate; > + else if (rate > pll->cfg->max_pll_rate) > + return pll->cfg->max_pll_rate; > else > return rate; > } > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > index 4fa73fbcba52..8306911f8318 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h > @@ -18,9 +18,6 @@ struct msm_dsi_pll { > bool pll_on; > bool state_saved; > > - unsigned long min_rate; > - unsigned long max_rate; > - > const struct msm_dsi_phy_cfg *cfg; > };
Restructure MSM DSI PHY drivers. What started as an attempt to grok the overcomplicated PHY drivers, has lead up to the idea of merging PHY and PLL code, reducing abstractions, code duplication, dropping dead code, etc. The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016, 28nm-lp) and lightly tested on RB3 (sdm845, 10nm). External dependency for sm8250: https://lore.kernel.org/linux-arm-msm/20210317144039.556409-10-dmitry.baryshkov@linaro.org/ The patch 'clk: fixed: add devm helper for clk_hw_register_fixed_factor()' is already a part of mainline as of 5.12-rc1, but is included here for completeness to fix compilation issues (as msm-next is based on 5.11-rc5). Changes since v1: - Rebase on top of msm/msm-next - Reorder patches to follow logical sequence - Add sc7180 clocks assignment - Drop sm8250 clocks assignment, as respective file is not updated in msm/msm-next Changes since RFC: - Reorder patches to move global clock patches in the beginning and dtsi patches where they are required. - remove msm_dsi_phy_set_src_pll() and guess src_pll_id using PHY usecase. The following changes since commit 627dc55c273dab308303a5217bd3e767d7083ddb: drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume (2021-03-22 18:52:34 -0700) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git dsi-phy-2 for you to fetch changes up to 0fec912264e9ee8f0ebbad12e2711843d7d9e0ac: drm/msm/dsi: stop passing src_pll_id to the phy_enable call (2021-03-24 18:14:39 +0300) ---------------------------------------------------------------- Daniel Palmer (1): clk: fixed: add devm helper for clk_hw_register_fixed_factor() Dmitry Baryshkov (27): clk: mux: provide devm_clk_hw_register_mux() clk: divider: add devm_clk_hw_register_divider drm/msm/dsi: replace PHY's init callback with configurable data drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* code drm/msm/dsi: drop multiple pll enable_seq support drm/msm/dsi: move all PLL callbacks into PHY config struct drm/msm/dsi: drop global msm_dsi_phy_type enumaration drm/msm/dsi: move min/max PLL rate to phy config drm/msm/dsi: remove msm_dsi_pll_set_usecase drm/msm/dsi: stop setting clock parents manually arm64: dts: qcom: sdm845: assign DSI clock source parents arm64: dts: qcom: sc7180: assign DSI clock source parents drm/msm/dsi: push provided clocks handling into a generic code drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks drm/msm/dsi: use devm_of_clk_add_hw_provider drm/msm/dsi: make save/restore_state phy-level functions drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy drm/msm/dsi: drop msm_dsi_pll abstracton drm/msm/dsi: drop PLL accessor functions drm/msm/dsi: move ioremaps to dsi_phy_driver_probe drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances drm/msm/dsi: remove temp data from global pll structure drm/msm/dsi: inline msm_dsi_phy_set_src_pll drm/msm/dsi: stop passing src_pll_id to the phy_enable call arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 + drivers/clk/clk-fixed-factor.c | 39 +- drivers/clk/clk-mux.c | 35 + drivers/gpu/drm/msm/Kconfig | 8 - drivers/gpu/drm/msm/Makefile | 9 - drivers/gpu/drm/msm/dsi/dsi.h | 58 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 -- drivers/gpu/drm/msm/dsi/dsi_manager.c | 29 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 150 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 41 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 745 ++++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 939 ++++++++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 16 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 654 +++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 479 +++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 772 +++++++++++++++- drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 184 ---- drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 132 --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 881 ------------------ drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 1096 ----------------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 643 ------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 526 ----------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 913 ------------------- include/linux/clk-provider.h | 34 +- 25 files changed, 3722 insertions(+), 4721 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c