mbox series

[v5,0/2] Add Synopsys High-Speed USB PHY driver for Qualcomm SoCs

Message ID 20181127100722.9993-1-shawn.guo@linaro.org
Headers show
Series Add Synopsys High-Speed USB PHY driver for Qualcomm SoCs | expand

Message

Shawn Guo Nov. 27, 2018, 10:07 a.m. UTC 
It's based on a downstream driver from Sriharsha Allenki <sallenki@codeaurora.org>
that uses USB phy framework, and gets rewrote to adpot generic phy
framework together with quite some cleanups.

Changes for v5:
 - Drop mb() call from function qcom_snps_hsphy_init_sequence() and
   qcom_snps_hsphy_por_reset().

Changes for v4:
 - Kill device tree property 'qcom,init-seq' by moving the settings
   into phy driver as device match data.

Changes for v3:
 - Use SoC specific compatible "qcom,qcs404-usb-hsphy".
 - Use OF graph instead of extcon bindings to model the link to USB
   connector.

Changes for v2:
 - Add a pointer to phy/phy-bindings.txt for property #phy-cells.
 - Roll back voltage settings in case function
   qcom_snps_hsphy_config_regulators() fails in the middle.
 - Add a comment for init-seq tuple which consists of 3 numbers.
 - Sort include headers alphabetically.
 - Sort register definitions in order of offset.

Shawn Guo (1):
  phy: qualcomm: Add Synopsys High-Speed USB PHY driver

Sriharsha Allenki (1):
  dt-bindings: phy: Add Qualcomm Synopsys High-Speed USB PHY binding

 .../phy/qcom,snps-28nm-usb-hs-phy.txt         |  87 +++
 drivers/phy/qualcomm/Kconfig                  |  10 +
 drivers/phy/qualcomm/Makefile                 |   1 +
 .../phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c  | 529 ++++++++++++++++++
 4 files changed, 627 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c

-- 
2.18.0

Comments

Jack Pham Dec. 19, 2018, 8:01 p.m. UTC | #1 
Hi Shawn,

On Tue, Nov 27, 2018 at 06:07:22PM +0800, Shawn Guo wrote:
> It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which

> is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.

> 

> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

> ---

>  drivers/phy/qualcomm/Kconfig                  |  10 +

>  drivers/phy/qualcomm/Makefile                 |   1 +

>  .../phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c  | 529 ++++++++++++++++++


Just caught this...
s/snsp/snps/ in the file name? The bindings doc in Patch 1 is named
correctly.

Thanks,
Jack
-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Shawn Guo Dec. 20, 2018, 12:48 a.m. UTC | #2 
On Wed, Dec 19, 2018 at 12:01:07PM -0800, Jack Pham wrote:
> Hi Shawn,

> 

> On Tue, Nov 27, 2018 at 06:07:22PM +0800, Shawn Guo wrote:

> > It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which

> > is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.

> > 

> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

> > ---

> >  drivers/phy/qualcomm/Kconfig                  |  10 +

> >  drivers/phy/qualcomm/Makefile                 |   1 +

> >  .../phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c  | 529 ++++++++++++++++++

> 

> Just caught this...

> s/snsp/snps/ in the file name? The bindings doc in Patch 1 is named

> correctly.


Oops, I will fix it with v6.  Thanks for spotting it.

Shawn